From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752281AbcAFIJb (ORCPT ); Wed, 6 Jan 2016 03:09:31 -0500 Received: from mail-am1on0063.outbound.protection.outlook.com ([157.56.112.63]:27328 "EHLO emea01-am1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751341AbcAFIJ3 (ORCPT ); Wed, 6 Jan 2016 03:09:29 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=hongxing.zhu@nxp.com; From: Richard Zhu To: , CC: Subject: [RFC 2/4] clk: imx7d: enable the mu and m4 root clocks Date: Wed, 6 Jan 2016 16:06:42 +0800 Message-ID: <1452067604-10466-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1452067604-10466-1-git-send-email-hongxing.zhu@nxp.com> References: <1452067604-10466-1-git-send-email-hongxing.zhu@nxp.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [123.151.195.53] X-ClientProxiedBy: SIXPR04CA0070.apcprd04.prod.outlook.com (10.141.119.28) To DBXPR04MB271.eurprd04.prod.outlook.com (10.141.10.147) X-Microsoft-Exchange-Diagnostics: 1;DBXPR04MB271;2:F5JkWer18Sdr9qXIC0sH6LzPuDM0dHf2+SeuY4hII6FqGNXyrSOmcHFe8BB8ohIuU0Z4RP0jcp/L8AN3lDlzA06Vn+1mOu9dLkR41gh+2oZKrpqEvZKF1taVvjkj/K05hTE+D510gzwgdQp2psKlIg==;3:UgOfYlaR3pKo8lCoIbsXnKcqU6ac2P9BWq/Vqec6X6RhMntWf1RgsqrqndFJfGNwkyCpMEI6RAXdL5xhoGl0HdeUxXZ32iE8aafWekzoUeO/YcYINRU8YPU4zebCOQ7V;25:0ocrSucUhPlriIwVPjRpe4cCAKPa7fhlCixOARnb/CTghRBUQ8/olUWls6SKAwtiBwPZb0XD9fBpBv5FdTxrTN5UBD4YI5i4e75mvk4mPTnS7P63yrEx0dzNY2iFKYLP+7cxhOQQ9+ZFsfBhkmIiODf9rpodbYerzrGulXQTeKDlcdiAR8CBjMwdZUAtaxLBvstG1zRa+CRthH3fYaM1AtiUp7o/753/V6xdZOHWr5GXoaDc4qoyp/sGOKcVc1+rjfx6KUKohs2UDLAxlH70Gg== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DBXPR04MB271; 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X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;DBXPR04MB271;23:f6HsCnhurMmdonLWh/l1kZmIQgcftWOnFSmhOB0wJy?= =?us-ascii?Q?4iFAAwj/kuOMOnwECYrnOQmNVAW1B3rb7e9cJFGsVgADVmeRH5uQwVJepf7h?= =?us-ascii?Q?RCKtN7zbkNYcI4E0BChNwz9EYw2Dsv7RjyuoilnibzAWPjunSwhLMEpM7oTY?= =?us-ascii?Q?TYgHSYD64I7mmwPhk0g0q31qQsdpSSz83+L54bXBxIEmEUp/vExQaNdOk+CP?= =?us-ascii?Q?dvIwHkAnPHL2UTDJehffsPT2eApP0NT4ISErXnHjfB1Kslb83snsLRBL+b0M?= =?us-ascii?Q?XGw0JDZwOFSrQF728E+H5/aRfU1n6vUUBbbTcRf6gy7bm0QVkJmXDslomHcH?= =?us-ascii?Q?Kb4ZJX64RdulgGKIKuuXAthPM0Tt5z+lkZoUEB4Bjhiy0RPDLd/s//kuyhRG?= =?us-ascii?Q?PKahUh2T2LTuSoCtHgrHI5vyVLFnFXQNXJgwsxzV6V2G2JjwpO2GV7YGYoH7?= =?us-ascii?Q?BiEQ1/rkytz8GE9r03NsDRuWcM1ZU82Nw9AnQOIGZAhxNe1OgKCLVKeLiRJu?= =?us-ascii?Q?esY0pFZ/B5o7+IslJbhXFu/+dDvbW/HIiuJozY6vbBi0aijmXL3cv8ZrZPtL?= =?us-ascii?Q?mcqWuk5+pE42aFR0baCuOsgsajLT2omgZaV7DNWSzxc+0GYQZGYFbySxKbXo?= =?us-ascii?Q?FzSr5qEK3pqwcfZ7Ge7g+nx6SZJbTfY7X64v4smiKodlVqaARPrkaa8Nmcn+?= =?us-ascii?Q?eBQdyVtrSZ1pq1CLttNYG/S9F77tAmmCVgDmUzrijJZcxcmTMrplsAsmTMsn?= =?us-ascii?Q?Y+D6OAMSKZl5xLn/Jez+jorTNojMReU0rfQmxULOd03d9YP2FasnBIUEgcZc?= =?us-ascii?Q?2YkBkba3SDrMGpCsfhM4HzIZnvGbVv1MlPJUd/Nz/lFIMCVfNDcZGGuzXHQQ?= =?us-ascii?Q?fi4gxq7TLt5YBnkJEVSQdIZQhiOtIgiqxfGgTGZt1eOPZGQlTd++y7DNK8f/?= =?us-ascii?Q?jkvmua+wgzomyF29Ru352xmfvne6IO/oNO49zUbHr0iewYNRjaT/3Md27uez?= =?us-ascii?Q?rMkxq4Qc+j+Ir4BQzviSjKlQUY4LH5FEBwaP9Xdd41jIlteUotbJXc85lGa8?= =?us-ascii?Q?cyH5A=3D?= X-Microsoft-Exchange-Diagnostics: 1;DBXPR04MB271;5:E6ifjXbWIZITOV4n5dfrX+yYyStjgXaYqKIaoKoiEoRHYIgiirGoBTH1oyeIXFC0j1OeQspl6Xu4fQVnkieiNXfj8CmqLQEOM0GwC7+IRXUCcWSo011nJ+xnwB1qryNmiyGsfKiByjWxMxsjdZgt0w==;24:RifhUZxG7sCvPsxV/c+nNx/X5whwWhcvEUc7QxB6BrrFCG1g3Vvk1d9/cUPbCVDaCKSA4m3CdA0UPygaHUpcz4LYdrJMcEmNZtVCZlhZ2oA= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2016 08:09:25.2950 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBXPR04MB271 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Richard Zhu enable the mu and m4 root clocks Signed-off-by: Richard Zhu --- drivers/clk/imx/clk-imx7d.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 448ef32..ac8288b 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -692,6 +692,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2); clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider("dram_post_div", "dram_cg", base + 0x9880, 0, 3); clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); @@ -769,6 +770,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); + clks[IMX7D_MU_ROOT_CLK] = imx_clk_gate2("mu_root_clk", "ipg_root_clk", base + 0x4270, 0); clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate2("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate2("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate2("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); @@ -870,5 +872,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) imx_register_uart_clocks(uart_clks); + /* set the parent clock source of m4, then keep it enabled */ + clk_set_parent(clks[IMX7D_ARM_M4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + clk_prepare_enable(clks[IMX7D_ARM_M4_ROOT_CLK]); + } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); -- 1.9.1