From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753662AbcALWKX (ORCPT ); Tue, 12 Jan 2016 17:10:23 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56163 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753629AbcALWKU (ORCPT ); Tue, 12 Jan 2016 17:10:20 -0500 Date: Wed, 13 Jan 2016 00:10:14 +0200 From: "Michael S. Tsirkin" To: linux-kernel@vger.kernel.org, Linus Torvalds Cc: Davidlohr Bueso , Peter Zijlstra , Ingo Molnar , Thomas Gleixner , "Paul E. McKenney" , the arch/x86 maintainers , Davidlohr Bueso , "H. Peter Anvin" , virtualization , Ingo Molnar , Arnd Bergmann , Andy Lutomirski , Borislav Petkov , Andrey Konovalov Subject: [PATCH v2 1/3] x86: drop mfence in favor of lock+addl Message-ID: <1452635935-5439-2-git-send-email-mst@redhat.com> References: <1452635935-5439-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452635935-5439-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org mfence appears to be way slower than a locked instruction - let's use lock+add unconditionally, same as we always did on old 32-bit. Signed-off-by: Michael S. Tsirkin --- arch/x86/include/asm/barrier.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index a584e1c..7f99726 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -15,11 +15,12 @@ * Some non-Intel clones support out of order store. wmb() ceases to be a * nop for these. */ -#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) + +#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) #else -#define mb() asm volatile("mfence":::"memory") +#define mb() asm volatile("lock; addl $0,0(%%rsp)" ::: "memory") #define rmb() asm volatile("lfence":::"memory") #define wmb() asm volatile("sfence" ::: "memory") #endif -- MST