From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756529AbcANWa7 (ORCPT ); Thu, 14 Jan 2016 17:30:59 -0500 Received: from mail-bn1bon0090.outbound.protection.outlook.com ([157.56.111.90]:16096 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754342AbcANWay (ORCPT ); Thu, 14 Jan 2016 17:30:54 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; From: Aravind Gopalakrishnan To: , , , , CC: , , , Aravind Gopalakrishnan Subject: [PATCH 0/5] Updates to AMD MCE driver per Scalable MCA spec Date: Thu, 14 Jan 2016 16:05:35 -0600 Message-ID: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BY1PR15CA0039.namprd15.prod.outlook.com (25.162.17.177) To BLUPR12MB0418.namprd12.prod.outlook.com (25.162.92.11) X-Microsoft-Exchange-Diagnostics: 1;BLUPR12MB0418;2:S+6F/sqsGE7T+VWA+6MbVTEMEQxvcwJydbdE94BYVV7JqmqgUow2CblGfRkPeg58cMAN3Tw92hVpW++ZaOKQEX8yrudYvU+BLY1YN9JZ5RcUcwdiwMUd3O+L66uJiQNcR8O9cTg2H9r9CN6LWdTaCg==;3:TJw21ytlY1ITM2j1OMUKp77YSZDW5Q+frVcP7sLR7Qf7iV6DTWh9vdpulNo8yyCLvGPx/LXp7j9I5Bo2/IVQl8VzaNyy7O8eGdMPUS2ydoSW0agIXEPlFdh1FUDrEI78;25:dGNKp5y8QdiUWYaip1c22gmnKT3VxBrHojQlYaB/DXXwoQtpWxr8+kp35rhaud1xjk3Hc6Jl9bImEtPUlBlLabFvvi5PTSjeanQZlsYK9vqRQZFP2Be3mvN4VbY2Zbk9/wSnMro9y2NoW0H022gaOOTNKBxdto2745UUUpV9aUlJYCpm70w6onPAG3/Onyv6NgSlptrIznua6oq5A6hDEmuaKsNrpVN9YL0fu32PrO/lOL6lLTz+pCfXgCzQusSe X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR12MB0418; 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Patches 1-3 include some minor changes to existing code and have been tested for regressions on older families. Patches 4-5 is new code and only runs on processors with ScalableMCA feature enabled (for future) Patch 1: Order of mce_amd_feature_init() was incorrect as it should be called after we gather features from cpuid bits. Fixing that in this patch Patch 2: We do not require shared bank verification on ZP. Modifying code here to return early if we are on a processor that supports SMCA feature. Patch 3: The number of blocks per bank is reduced from Fam17h onwards. Fixing code to reflect this architectural change Patch 4: LVT offset for thresholding is now programmed in different MSR as opposed to per-bank MISC register in earlier processors. Fixing code here to obtain LVT offset from correct MSR. Patch 5: OS is required to set MCAXEn bit in the per-bank CONFIG MSR to acknowledge the use of new MSR range for MCA. Doing that here and also creating definitions for the new MSR range in msr-index. Note: checkpatch generates warnings for Patch 5. But I have not wrapped text around the character limit as it looked ugly. (I overshot it by only a character or two) Aravind Gopalakrishnan (5): x86, mce: Fix order of AMD MCE init function call x86/mcheck/AMD: Do not perform shared bank check for future processors x86/mcheck/AMD: Reduce number of blocks scanned per bank x86/mcheck/AMD: Fix LVT offset configuration for thresholding x86/mcheck/AMD: Set MCAX Enable bit arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++ arch/x86/kernel/cpu/mcheck/mce.c | 2 +- arch/x86/kernel/cpu/mcheck/mce_amd.c | 50 ++++++++++++++++++++++++++++++++++-- 3 files changed, 72 insertions(+), 3 deletions(-) -- 2.7.0