From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754765AbcANV5y (ORCPT ); Thu, 14 Jan 2016 16:57:54 -0500 Received: from mail-bl2on0077.outbound.protection.outlook.com ([65.55.169.77]:14752 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753907AbcANV5v (ORCPT ); Thu, 14 Jan 2016 16:57:51 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; From: Aravind Gopalakrishnan To: , , , , CC: , , , Aravind Gopalakrishnan Subject: [PATCH 4/5] x86/mcheck/AMD: Fix LVT offset configuration for thresholding Date: Thu, 14 Jan 2016 16:05:39 -0600 Message-ID: <1452809140-3328-5-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BY1PR15CA0039.namprd15.prod.outlook.com (25.162.17.177) To BLUPR12MB0418.namprd12.prod.outlook.com (25.162.92.11) X-Microsoft-Exchange-Diagnostics: 1;BLUPR12MB0418;2:o7gNBPo72H4oKBOICRCK7aLyAp9be8VEX18OPVO4Adtl3EZmxJMdP2QrYDgsHg/+CU78ifeRlDL+8nBZWgZDrxwx5rFvhfNsp1+0sv3UAwSkZppRFNxErnxeSkvpusqG86IkRWkVPuitKwvPOu4VyA==;3:ErtQlZq+UqWGnRYHIRCjTg1iZ5qN0BdLg0NVnJJOT0gS9OmVU0VzSobfjtYB7+jA0XRU2WTZF0qBJ6gimW3uFSO1zBbs6GO+LouMTK5+EW9/euWEynarnH+7u5WzVl6H;25:107PTPVxgwYHmLkCe8Ct7HUPD7ZjytgLBFQhMpihWOLYfL3AYNxk6EsbJh3AlLTlqSmC+yIrIGZrk/KiRH39fi6laxPfPrpVY2mewQA/NEJGpSBsj+JZPc2qHqm/l35RZXKS7vOV7aWBed2n0o3PyA4iu6TbtXzJfVEciXrB+z92LvWThj42KFrLFH6Y+iVFvhlzvKXtaz/u2DV+/1/4H8jeGhJf5KWkmWorC0gyGnrPKwz80ySHMYc6daQQReue X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR12MB0418; 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Fixing the code here to obtain the LVT offset from the correct MSR for those families which have SMCA feature enabled. Signed-off-by: Aravind Gopalakrishnan --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index e650fdc..4383d75 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -49,6 +49,9 @@ #define DEF_LVT_OFF 0x2 #define DEF_INT_TYPE_APIC 0x2 +/* SMCA settings */ +#define SMCA_THR_LVT_OFF 0xF000 + static const char * const th_names[] = { "load_store", "insn_fetch", @@ -143,6 +146,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) } if (apic != msr) { + /* + * For SMCA enabled processors, LVT offset is programmed at + * different MSR and BIOS provides the value. + * The original field where LVT offset was set is Reserved. + * So, return early here. + */ + if (mce_flags.smca) + return 0; + pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); @@ -301,7 +313,21 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) goto init; b.interrupt_enable = 1; - new = (high & MASK_LVTOFF_HI) >> 20; + + if (mce_flags.smca) { + u32 smca_low = 0, smca_high = 0; + + /* Gather LVT offset for thresholding */ + if (rdmsr_safe(MSR_CU_DEF_ERR, + &smca_low, + &smca_high)) + break; + + new = (smca_low & SMCA_THR_LVT_OFF) >> 12; + } else { + new = (high & MASK_LVTOFF_HI) >> 20; + } + offset = setup_APIC_mce_threshold(offset, new); if ((offset == new) && -- 2.7.0