From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754873AbcANV5z (ORCPT ); Thu, 14 Jan 2016 16:57:55 -0500 Received: from mail-bl2on0077.outbound.protection.outlook.com ([65.55.169.77]:14752 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751189AbcANV5x (ORCPT ); Thu, 14 Jan 2016 16:57:53 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; From: Aravind Gopalakrishnan To: , , , , CC: , , , Aravind Gopalakrishnan Subject: [PATCH 5/5] x86/mcheck/AMD: Set MCAX Enable bit Date: Thu, 14 Jan 2016 16:05:40 -0600 Message-ID: <1452809140-3328-6-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1452809140-3328-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BY1PR15CA0039.namprd15.prod.outlook.com (25.162.17.177) To BLUPR12MB0418.namprd12.prod.outlook.com (25.162.92.11) X-Microsoft-Exchange-Diagnostics: 1;BLUPR12MB0418;2:bYbteIh+A9+CBtPKsHI7SIBNSAgLsAoSKoHuq11fO61Y02nSWWAenHuNvJObWGuGq3OjHdW9PaAdGQeZYX5VL40zwkSPaV/oNTLjCI8mdHM35CTPYoZSU6smYeX84FZvdcngdwrzETzlmxjS7NfZMA==;3:UrMLDHQkkgeHNGu8XEqOBfwSjGBLL0Vdh05dLWd+JCcY2BgCKhaou+4XZmJkO1e8/Ct5JFsxg3V9Rt7CSjHSywBy35qNpQ0Vc8eIe0wALfxalMx+SK8GKyR1Ug4q/9b0;25:wwDrgo0Aqh916OGf+R8A05QgS7pbrzVeWlUMEI6MxTEWETmvn8was0Y57lvum6n2PDXuRjSBPAWSQO3dX0hmLHGS0Ou44aNhUS5jRxhfBlVQ2eLzJNWJodeEWUt8XEFPhMM0vUkgtuxas3G4DNtIw57TQdoA7orQhpqzp9Wn2vG4UCK1PDf2jKZzx+qqpp2eOTeyY2QcDpnid233cLvuv6mUXVpwHo+GZibRHhaA1nACZHcRO1h9kYtXCMgJT+D5 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR12MB0418; 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If it is not set, then all UC errors will cause a system panic. So setting the bit here and also defining the new MSR range for SMCA enabled proccessors in msr-index Signed-off-by: Aravind Gopalakrishnan --- arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++++++++ arch/x86/kernel/cpu/mcheck/mce_amd.c | 12 ++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b05402e..88505f8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -264,6 +264,29 @@ #define MSR_IA32_MC0_CTL2 0x00000280 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) +/* SMCA defined MSR register set for AMD64 */ +#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000 +#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001 +#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002 +#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 +#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 +#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 +#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006 +#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 +#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 +#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a + +#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) + #define MSR_P6_PERFCTR0 0x000000c1 #define MSR_P6_PERFCTR1 0x000000c2 #define MSR_P6_EVNTSEL0 0x00000186 diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 4383d75..ae6fcca 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -51,6 +51,7 @@ /* SMCA settings */ #define SMCA_THR_LVT_OFF 0xF000 +#define SMCA_MCAX_EN_OFF 0x1 static const char * const th_names[] = { "load_store", @@ -316,6 +317,17 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) if (mce_flags.smca) { u32 smca_low = 0, smca_high = 0; + u32 smca_addr = 0; + + /* Set MCAXEnable bit for each bank */ + smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); + if (rdmsr_safe(smca_addr, + &smca_low, + &smca_high)) + continue; + + smca_high = (smca_high & ~SMCA_MCAX_EN_OFF) | 0x1; + wrmsr(smca_addr, smca_low, smca_high); /* Gather LVT offset for thresholding */ if (rdmsr_safe(MSR_CU_DEF_ERR, -- 2.7.0