From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753483AbcAOXn7 (ORCPT ); Fri, 15 Jan 2016 18:43:59 -0500 Received: from mail-bl2on0063.outbound.protection.outlook.com ([65.55.169.63]:8288 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752378AbcAOXm2 (ORCPT ); Fri, 15 Jan 2016 18:42:28 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; From: Aravind Gopalakrishnan To: , , , , CC: , , Subject: [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec Date: Fri, 15 Jan 2016 17:50:31 -0600 Message-ID: <1452901836-27632-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BLUPR13CA0045.namprd13.prod.outlook.com (25.160.82.16) To CY1PR12MB0427.namprd12.prod.outlook.com (25.163.91.17) X-Microsoft-Exchange-Diagnostics: 1;CY1PR12MB0427;2:puh47cXSwfbRgphpuhwGnRFVwndFU9SY9B3AZrkycx49It0dzYD6df9K6E+Gl96Yxo0vViurWgsyJXYiryW0CDUVVgz1RlO4lV5XpzxO1H7WQQu6O+Uy4qYHsxC35JYAZKxUsu4Uaet1lrnKxNvnIg==;3:l7stRf+VzzIUko0X9EtUY6SuWBeeHKi1l0Wz5opr7HCfKzUtBxU1jyaZNGcU4kfq8gUkOgw7v8EWvFbSqHfoqMJ5UThl5pEcyfPAuH6A5G0QytJmhw5xsXKc+n/9Er4o;25:sOKbCT5b9Hup+H7LpI4f4PD2Ecr5cxpcwfuSARwtGbzadvwvOgz/ELw2gcVeGUaFx7znFHXS5+p2mw4Di5zU8uJ5S+gRLtk8/OXbKyyJRprI3S1u1YzWZrvfjmTIMo7Va273MkbYlvcjRLC2SsX9r7Q38ICongaNDhkLWPmxv0+vQubtr+VGktdXJGj9GZQvU5pTWu5cmgd46ObShJLylk/atwkednnQhfFvayO+FYMz6lTmFurndNu63Ba9h+o+ X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR12MB0427; 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Patches 1-3 include some minor changes to existing code and have been tested for regressions on older families. Patches 4-5 is new code and only runs on processors with ScalableMCA feature enabled (for future) Patch 1: Order of mce_amd_feature_init() was incorrect as it should be called after we gather features from cpuid bits. Fixing that in this patch Patch 2: We do not require shared bank verification on ZP. Modifying code here to return early if we are on a processor that supports SMCA feature. Patch 3: The number of blocks per bank is reduced from Fam17h onwards. Fixing code to reflect this architectural change Patch 4: LVT offset for thresholding is now programmed in different MSR as opposed to per-bank MISC register in earlier processors. Fixing code here to obtain LVT offset from correct MSR. Patch 5: OS is required to set MCAXEn bit in the per-bank CONFIG MSR to acknowledge the use of new MSR range for MCA. Doing that here and also creating definitions for the new MSR range in msr-index. Changes in V2 (per Boris) - Include only definitions on header file that we are using here - Add comments around macros that belong to SMCA Aravind Gopalakrishnan (5): x86, mce: Fix order of AMD MCE init function call x86/mcheck/AMD: Do not perform shared bank check for future processors x86/mcheck/AMD: Reduce number of blocks scanned per bank x86/mcheck/AMD: Fix LVT offset configuration for thresholding x86/mcheck/AMD: Set MCAX Enable bit arch/x86/include/asm/msr-index.h | 5 +++ arch/x86/kernel/cpu/mcheck/mce.c | 2 +- arch/x86/kernel/cpu/mcheck/mce_amd.c | 63 ++++++++++++++++++++++++++++++++++-- 3 files changed, 67 insertions(+), 3 deletions(-) -- 2.7.0