From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753318AbcAOXnE (ORCPT ); Fri, 15 Jan 2016 18:43:04 -0500 Received: from mail-bl2on0063.outbound.protection.outlook.com ([65.55.169.63]:8288 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752751AbcAOXmi (ORCPT ); Fri, 15 Jan 2016 18:42:38 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; From: Aravind Gopalakrishnan To: , , , , CC: , , Subject: [PATCH V2 5/5] x86/mcheck/AMD: Set MCAX Enable bit Date: Fri, 15 Jan 2016 17:50:36 -0600 Message-ID: <1452901836-27632-6-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1452901836-27632-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1452901836-27632-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BLUPR13CA0045.namprd13.prod.outlook.com (25.160.82.16) To CY1PR12MB0427.namprd12.prod.outlook.com (25.163.91.17) X-Microsoft-Exchange-Diagnostics: 1;CY1PR12MB0427;2:oSShr2+E1iWZu5z5XjT40Kz4Htg0A0eU338lpG2j44g1NNyRjoWrAbWvukmyU17qw2HiN4V84W4LpQFs209MyTIVypYYJPvY/wrqWhnWSOm/GNLMYLVymxjOuvzKqyiaAKpNLrd+ff/Vegs7h94EWw==;3:7B+Tt40wUWBz4OnNsw25yU9rMVsTwcigsnigFB+qG5T45osNzNCh2NxfGo7W/ktMZ/iXHmNLjlGBXFNdOvAp+sUF9j3t/DTe/Z1DM1/+kg2UyeMl64Rtalrt7CHGe2Cy;25:Z+4yFZIuqJobSrXFMD1ktDtc9pGNrmuyJs1L6xbZ74QnGKxOBDhnsFLQAFLlh6TNlxy4Su7bqsey3+e7gU7FRbzXrhBAU9PNNED/d6laFdpoHlNKSZJCL/E+fcpnZr1p1V0aL55Rfvs+QU1JbzgnC+u95/za819d0VpoRRxPZF2fnVqax8Uc37kMJJMS0pMy9yVURMe+BWyyZCac4zl+igcM1tmsPrfTbVqQAoMR2sPmyREsdp38P7alMSmrIt4c X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR12MB0427; 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If it is not set, then all UC errors will cause a system panic. So setting the bit here and also defining the new MSR range for SMCA enabled proccessors in msr-index Signed-off-by: Aravind Gopalakrishnan --- arch/x86/include/asm/msr-index.h | 5 +++++ arch/x86/kernel/cpu/mcheck/mce_amd.c | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b05402e..088b5a7 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -264,6 +264,11 @@ #define MSR_IA32_MC0_CTL2 0x00000280 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) +/* SMCA defined MSR register set for AMD64 */ +#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 + +#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) + #define MSR_P6_PERFCTR0 0x000000c1 #define MSR_P6_PERFCTR1 0x000000c2 #define MSR_P6_EVNTSEL0 0x00000186 diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 29a7688..158ea86 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -57,6 +57,14 @@ /* Threshold LVT offset is at MSR0xC0000410[15:12] */ #define SMCA_THR_LVT_OFF 0xF000 +/* + * OS is required to set the MCAX bit to acknowledge + * that it is now using the new MSR ranges and new registers + * under each bank. It also means that OS will configure + * Deferred errors in the new MCx_CONFIG register. + * If the bit is not set, UC errors will cause a system panic + */ +#define SMCA_MCAX_EN_OFF 0x1 static const char * const th_names[] = { "load_store", @@ -322,6 +330,17 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) if (mce_flags.smca) { u32 smca_low = 0, smca_high = 0; + u32 smca_addr = 0; + + /* Set MCAXEnable bit for each bank */ + smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); + if (rdmsr_safe(smca_addr, + &smca_low, + &smca_high)) + continue; + + smca_high |= SMCA_MCAX_EN_OFF; + wrmsr(smca_addr, smca_low, smca_high); /* Gather LVT offset for thresholding */ if (rdmsr_safe(MSR_CU_DEF_ERR, -- 2.7.0