From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933886AbcATILD (ORCPT ); Wed, 20 Jan 2016 03:11:03 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:54831 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933521AbcATIKs (ORCPT ); Wed, 20 Jan 2016 03:10:48 -0500 From: Jisheng Zhang To: , , , , , , , CC: , , , , , Jisheng Zhang Subject: [PATCH 0/4] net: mvneta: support more than one clk Date: Wed, 20 Jan 2016 16:06:19 +0800 Message-ID: <1453277183-5412-1-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.7.0.rc3 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-01-20_03:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=1 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310008 definitions=main-1601200146 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms may provide more than one clk for the mvneta IP, for example Marvell BG4CT provides "core" clk for the mac core, and "axi" clk for the AXI bus logic. This series tries to addess the "more than one clk" issue. Note: to support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't have mbus concept etc. Jisheng Zhang (4): net: mvneta: sort the headers in alphabetic order net: mvneta: Try to get named core clock first net: mvneta: mmc: get optional axi clk net: mvneta: update clocks property and document additional clock-names .../bindings/net/marvell-armada-370-neta.txt | 6 +++- drivers/net/ethernet/marvell/mvneta.c | 36 ++++++++++++++-------- 2 files changed, 28 insertions(+), 14 deletions(-) -- 2.7.0.rc3