From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752137AbcA0EKe (ORCPT ); Tue, 26 Jan 2016 23:10:34 -0500 Received: from ozlabs.org ([103.22.144.67]:42183 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750851AbcA0EKc (ORCPT ); Tue, 26 Jan 2016 23:10:32 -0500 Message-ID: <1453867831.12023.0.camel@ellerman.id.au> Subject: Re: [PATCH] powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8 From: Michael Ellerman To: Madhavan Srinivasan Cc: benh@kernel.crashing.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Wed, 27 Jan 2016 15:10:31 +1100 In-Reply-To: <1453710826-3160-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1453710826-3160-1-git-send-email-maddy@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.16.5-1ubuntu3.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2016-01-25 at 14:03 +0530, Madhavan Srinivasan wrote: > Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to > remove assumption of MMCRA[SLOT] with respect to > PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also > specifies that Power8 does not support MMCRA[SLOT]. > But still PPMU_HAS_SSLOT flag managed to get into > Power8 code. Patch to remove the same from Power8 flags. > > Signed-off-by: Madhavan Srinivasan Thanks. I cleaned up and expanded the change log: powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8 Commit 7a7868326d77 ("powerpc/perf: Add an explict flag indicating presence of SLOT field") introduced the PPMU_HAS_SSLOT flag to remove the assumption that MMCRA[SLOT] was present when PPMU_ALT_SIPR was not set. That commit's changelog also mentions that Power8 does not support MMCRA[SLOT]. However when the Power8 PMU support was merged, it errnoeously included the PPMU_HAS_SSLOT flag. So remove PPMU_HAS_SSLOT from the Power8 flags. mpe: On systems where MMCRA[SLOT] exists, the field occupies bits 37:39 (IBM numbering). On Power8 bit 37 is reserved, and 38:39 overlap with the high bits of the Threshold Event Counter Mantissa. I am not aware of any published events which use the thereshold counting mechanism, which would cause the mantissa bits to be set. So in practice this bug is unlikely to trigger in practice. Fixes: e05b9b9e5c10 ("powerpc/perf: Power8 PMU support") Signed-off-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman cheers