From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754583AbcA2IbO (ORCPT ); Fri, 29 Jan 2016 03:31:14 -0500 Received: from mail-by2on0077.outbound.protection.outlook.com ([207.46.100.77]:56736 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754419AbcA2IbJ (ORCPT ); Fri, 29 Jan 2016 03:31:09 -0500 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=permerror action=none header.from=amd.com; X-WSS-ID: 0O1PGZR-07-BIO-02 X-M-MSG: From: Huang Rui To: Borislav Petkov , Peter Zijlstra , "Ingo Molnar" , Andy Lutomirski , "Thomas Gleixner" , Robert Richter , Jacob Shin , Arnaldo Carvalho de Melo , "Kan Liang" CC: , , , Suravee Suthikulpanit , Aravind Gopalakrishnan , Borislav Petkov , Fengguang Wu , Huang Rui Subject: [PATCH 2/2] perf/x86/msr: Add AMD instructions retired performance counter Date: Fri, 29 Jan 2016 16:29:57 +0800 Message-ID: <1454056197-5893-3-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454056197-5893-1-git-send-email-ray.huang@amd.com> References: <1454056197-5893-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(428002)(199003)(189002)(33646002)(53416004)(2906002)(4326007)(586003)(3470700001)(106466001)(229853001)(5001770100001)(105586002)(189998001)(11100500001)(5008740100001)(77096005)(5003600100002)(50226001)(50986999)(87936001)(36756003)(101416001)(47776003)(86362001)(575784001)(2950100001)(19580395003)(1220700001)(1096002)(92566002)(48376002)(5003940100001)(19580405001)(50466002)(76176999);DIR:OUT;SFP:1101;SCL:1;SRVR:BN4PR12MB0849;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;BN4PR12MB0849;2:OVG1Ltvnm7iNRnEo8LUkRvL7jGp5Jakd02343eeymdhGNUo2eiiPcsYvqahV7MEbWTTNPjIx+dGdDycwEuWM5MS9KJHX1t+J3QlCoJ9i2sKcSLSiQED9ryjk+F3W5Bn+bY2giAeyMx28tVmJCJw4Lg==;3:n1B7q5HPqfGlqM75TncV2uQZYMB9dyOipJyrh32zdEfK/paJtk5L84Bof64m2eDo8Y00wUaFaqlAXzOrTIWdGd5r44EDM13gaemL4Lm9NjDtEaxfnLrzpDJZSpJ1jx/jbTcqqEBEGFsH0nxugrTcD8YxGw7bm6kiiZNR2fpCvrPUYKeZ1/CzOYenAYvKWofbGJiZrgAzFbBjAQUh/IsuG4eTsjwjuIm+7PveoSPKpOY=;25:uDOE/ZhRB0iWPl/2oj4F9zfvUyJ5+AXC2RVmRdBtjkUgpzNlVLjhcaRNkPtQ4fXG5UhNJoEz0pGFzTeYL+hoX2p4wUurXxQ4oeVctBisNjpZk0uS89fYHqyb1p7ztQJObHT9/zU83D5h7gzrzjRIc9qH71YFHe7IRTyrQGBLWi1+6vCoagNKWRL68mrGgnU0ULdbNQmjZNJjCLFIbvjrJNZCC6gDDEFIM4lMH4VCkQ8x6oDtiizU6IOlyvJZChBO X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN4PR12MB0849; X-MS-Office365-Filtering-Correlation-Id: cd06005e-3e45-4800-de11-08d328868813 X-Microsoft-Exchange-Diagnostics: 1;BN4PR12MB0849;20:MN03kwkCUM2mx4Y6syeHunDFf/Prdcs8MkDNN7uDRyZDwdIJ/sK+fzRp4W/1gfGY53u1UScWgwE3aiIRgd0IQOF5BAakYiz24HYeA5TuC4Ff0JJixjUAfDu2qH1bUuSHXFn8/mNZ8WpLRRWkbBYlMdaW/HeH3WQSSKg43iTSsuSR46wt85FjBWQprF6CLvExMDSbB1HFwwN9lI1RpPK2yVrtTO4eOvPxuLdD4raq56QJWAAaMFCLllYHUaC3Itx9JWpYwD/QZBTyrO/vMBo+Ww2wiCYZuvEx/xrY7YHQHuwNxDb4Tf3jKN3pNu4pa00MIS9g0eRTGm0MJaZdcZt+fW8GyFeecSJg84rT9kCtQ7iHV6EIy3gk3R1fKMvdK0HhBHVp9dZw18kZzrt0DqqDeReRFYEiQsC0QsLHXkZSSWSl8TPAoiV4xsVL9GQMs4wBor5VWMge53mu2TRljAKtbbIKrXxlYQLiGYMBbzDnS1THJ6qDAzEe3d9EAoGlBNiw X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13018025)(13017025)(13023025)(13015025)(8121501046)(5005006)(13024025)(10201501046)(3002001);SRVR:BN4PR12MB0849;BCL:0;PCL:0;RULEID:;SRVR:BN4PR12MB0849; X-Microsoft-Exchange-Diagnostics: 1;BN4PR12MB0849;4:Os0pDf47EzdKz+u6sBf+/1sVwk9oyucHU9/DA1CasgjRuCSZo0UIWxREeKvLsMlvh66CYwgvlEfQZthoPoWgpt9qY0G22Ad0cSgS5gDbjtZT0I0tv5DT3P/GkkRj731GagX3KhPMMH6RA1d4yP3YtwY1cCLKzh38YET3fuEYiErwFNisVZE2AbqCsk+wElyKjd4SNesc17e8dJSkETEDVSA0/2qG5E3Jds7P78KoxLU5Z+R+6ucgbRa7w9DrtDnp8ZTCIoqWLGPap6frpoK/3WVM882VUoPgCtIuExyC1hN0MPy/ljJKCGiUcCAlZavXyAEa8SI9z3/Cy1ZuJV4bwKyB3m8bLc9GWAKeDitJEbxo75S2vJeNJ/dtQaZTLOJlDmHmx3YYfTNQJ638ez0ctwDOpltOj946FmVvw5iLV112rwpqhCM5eNH68TGa8xbl+MZuDjBgAiImal8ayDFBATtxIIaWq5eaKRpsZDUestrP5w2DFtCM2ecYLiZPNwgH X-Forefront-PRVS: 083691450C X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;BN4PR12MB0849;23:zw1BIHsfNAOOzlObdrUd0uWh994KUWrL0U3Bj3/JF?= =?us-ascii?Q?Cn8Up71CPr1ibEuxpmbvj3f5Ah3YAoYKGs6cRmfNMYD6p2EbTUO/T1GV2vYe?= =?us-ascii?Q?GQlLOXmPYh6uR6S0FCJF0QpD20WQe2qwf6pUtZyJ0OBkKByTTRyFCkSj1gVd?= =?us-ascii?Q?oe9x6rv2MXNnxSH9lgIdBPQXEbxusxOu+zPyXuUq1TutiGHYUNP7dWYH78Z2?= =?us-ascii?Q?VujuECfcw1wROwsovuVYK3R+QlOS9qm1BlF+SXAw9hDjsqFc+Le4UDzw+iH3?= =?us-ascii?Q?iLf7VrOrSkd+1T3FrsTLlWwC9IJFIGa7op71maNlUPzCsNWuUIorJlsBbk93?= =?us-ascii?Q?G9OpXb13mZUzFkIkhyS78XhnstfjkXePi/l5Dsr1HDfY9lqQgs8FDcp6AF01?= =?us-ascii?Q?sxq770seY3Z0g1doV4M8FUJSS3os6Xb9tokc6YhHZ65SZBBtUs/cm14OHGhj?= =?us-ascii?Q?kqMK0dEMzk3fL5LTlMDFZS75sggIFgojBUbL5PPRYioZV0FGAQwdmnLS1dYF?= =?us-ascii?Q?QSttWuBntDZA+dJO8uJreRyiz2hhZJtEwatn5NumBPBKNSAwwxfoVPMWvpMM?= =?us-ascii?Q?NdGLMMQdhuOTtkCHBM1shwkKkkUq2bUohEEVACrVbz1H++regKiS6DLBPGoz?= =?us-ascii?Q?zywVKSFQZLCZYhoGR5iBIi8350J8jOj4MADRC9mBkHXdMZG1UHftxtw3RyO+?= =?us-ascii?Q?SofI1V2fdBnKPvu0/KHVR+/pG+9LDC5PWrolsn2o+4IMMNJ2gtr0UzeuVfpo?= =?us-ascii?Q?6V48tdBomawIAx2GFBPI4o4Q++c6eiYVwOQWMONa6zWAp/9LuFlpfI2yL91r?= =?us-ascii?Q?dJNttsSS960i0LLeYJCkN+aHiUhH3CXEjrf/oTOMfI4lD948DK3b/RqJj+C3?= =?us-ascii?Q?7uCLHHa8Ul4+ovHDnqjUyWBX24aQJNO0oIrSN4YcoAEnDB1dEPzH2L27SzaM?= =?us-ascii?Q?puLf+v4jyF5ci0llN5TkN1ebt4kSMf8nw5O1a0UAyZATJwT0Pscnj+QasJjb?= =?us-ascii?Q?Qs9gK+5UlAFNxukWsOpSZyvgKlF0eAmncxE/IGxhZ2i7w=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1;BN4PR12MB0849;5:RT+f4wz4jWcjWYLZlOXVHTrX9dxA8XGM8qSkyk+wDBlE0j/pbnRAsG40HYP8Fan06QErkrISaaHj9xsIEOJJanAue8u0SKLmWVDKmC0i3Fh5Jn532drdAbQ8NC86FUDYSWcmxu/h8LgxAZXUVMrGTA==;24:7TnAFlY0uguGFMT+fhTMlQxW+Dy25gjycpDogG4+0K3QEMMqovQ1CLKzMSDjsOMxsrf8c2SlE7a93YQ2T0zDDMsk0oqTh1V2T5UccMGilMw=;20:HmYc/0ZvfYWj0fQL6wcCEBucIr8pBkQUsVYOQcuFj2zLHSf+ulul9r0Rucwx5/CGbirRgriqhAK7MJoq2SGIpw3wbq3Uuquost6rXas5BB6qIRCrUGoUJRKHwMPTp3PD2rtSNWwdrGCQCXIlZyAmYRfFw4x1NeQRsEFt+PF4ja+pxYSEIXx9uzlbKz118Yfd5OXjlTh5jryV3fsat9B3kTJee3aVfm0w1evdzeL29k8DIwlzuM3yP9//zo08lY9E SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2016 08:31:05.4041 (UTC) X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN4PR12MB0849 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which indicated by CPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register (MSR 0xC000_000E9) increments on once for every instruction retired. Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kernel/cpu/perf_event_msr.c | 30 +++++++++++++++++++----------- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1f9d682..a0ec7cc 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -259,6 +259,7 @@ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ +#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ /* * BUG word(s) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0e873e3..982dcda 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -308,6 +308,9 @@ #define MSR_AMD64_IBSOPDATA4 0xc001103d #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ +/* Fam 17h MSRs */ +#define MSR_F17H_IRPERF 0xc00000e9 + /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL 0xc0010230 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 diff --git a/arch/x86/kernel/cpu/perf_event_msr.c b/arch/x86/kernel/cpu/perf_event_msr.c index 6f6772f..7111400 100644 --- a/arch/x86/kernel/cpu/perf_event_msr.c +++ b/arch/x86/kernel/cpu/perf_event_msr.c @@ -7,6 +7,7 @@ enum perf_msr_id { PERF_MSR_PPERF = 3, PERF_MSR_SMI = 4, PERF_MSR_PTSC = 5, + PERF_MSR_IRPERF = 6, PERF_MSR_EVENT_MAX, }; @@ -21,6 +22,11 @@ static bool test_ptsc(int idx) return boot_cpu_has(X86_FEATURE_PTSC); } +static bool test_irperf(int idx) +{ + return boot_cpu_has(X86_FEATURE_IRPERF); +} + static bool test_intel(int idx) { if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -75,20 +81,22 @@ struct perf_msr { bool (*test)(int idx); }; -PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); -PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); -PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); -PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); -PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); -PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); +PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); +PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); +PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); +PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05"); +PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06"); static struct perf_msr msr[] = { - [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, - [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, - [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, - [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, - [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, + [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, + [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, + [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, + [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, + [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, }, + [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, }, }; static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { -- 1.9.1