From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932945AbcBAOm4 (ORCPT ); Mon, 1 Feb 2016 09:42:56 -0500 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:48136 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932609AbcBAOmz (ORCPT ); Mon, 1 Feb 2016 09:42:55 -0500 From: Chen-Yu Tsai To: Maxime Ripard , Michael Turquette , Stephen Boyd Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 0/2] clk: sunxi: Fix APBS clock for Allwinner A80 Date: Mon, 1 Feb 2016 22:42:47 +0800 Message-Id: <1454337769-4130-1-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.7.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi everyone, When I did the A80 PRCM support, I failed to notice the A80's APBS clock was not the same as the A23's APB0 clock. The former is a zero-based divider, while the latter is a power-of-two divider. But the lowest 2 dividers are the same. The hardware defaults to the lowest setting, or a /1 divider. Since the child gates do not propagate clk_set_rate up, and no consumers here do clk_set_rate, this actually works. I realized my mistake while reviewing the A83T's PRCM patches. The A83T shares the same PRCM clocks as the A80. Regards ChenYu Chen-Yu Tsai (2): clk: sunxi: Add support for A80 APBS clock ARM: dts: sun9i: Fix apbs clock compatible Documentation/devicetree/bindings/clock/sunxi.txt | 1 + arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- drivers/clk/sunxi/Makefile | 2 +- drivers/clk/sunxi/clk-sun9i-apbs.c | 64 +++++++++++++++++++++++ 4 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/sunxi/clk-sun9i-apbs.c -- 2.7.0