From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753845AbcBATYS (ORCPT ); Mon, 1 Feb 2016 14:24:18 -0500 Received: from mail-db5eur01on0044.outbound.protection.outlook.com ([104.47.2.44]:54916 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753561AbcBATYP (ORCPT ); Mon, 1 Feb 2016 14:24:15 -0500 Authentication-Results: spf=fail (sender IP is 212.179.42.66) smtp.mailfrom=ezchip.com; lists.infradead.org; dkim=none (message not signed) header.d=none;lists.infradead.org; dmarc=none action=none header.from=ezchip.com; From: Noam Camus To: CC: , , , , Noam Camus Subject: [PATCH 0/2] Adding NPS400 drivers Date: Mon, 1 Feb 2016 21:22:46 +0200 Message-ID: <1454354568-15055-1-git-send-email-noamc@ezchip.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-22106.002 X-TM-AS-Result: No--4.778000-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;DB3FFO11FD031;1:EUTyEpZ9OSF8QKV6lvV54UmLhQxlPfq/u8HbOgoFzii8BxDmICgGrYrDlh1Hd22GkOPmfMC3v0YQsiru8317qCXaDPiYenrt99ubncf+qDBowXRm7TXBlFW2vLoJ9NVwGZVKdDEGzOhGsiOUE3zYAcKSlcK6VdriV+AfTSKI63JJJXRYIp2fhUioL0Fer03jIKvIRJMOSqyNX85FZPxVb0xtLp0WelrPA1KECwksFDBYhmBNZ0DfBGbiJt0YLaQCGpMnnprCLDWWDGkg86GXSqa+rUrgmHjVz4CZwqD3P7c7FNKUdOuN7dw94dV3jjuklsq+MQElEPdzqd3eEBGpC+WdFSHXj3g5uFjMJ+Dohcn98rsP3F+ZZdiCpTvXI1njam62W4oMn8+Nc5fV5WRqKtb7p+fwE3mpKSqBJXzky8g2sIPbgwH5RCFux62F/3EIHNnkL/SV1V90qC+Qy84txw== X-Forefront-Antispam-Report: CIP:212.179.42.66;CTRY:IL;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(11100500001)(2351001)(106466001)(15975445007)(92566002)(4326007)(77096005)(86362001)(5008740100001)(1220700001)(5001970100001)(107886002)(110136002)(586003)(50226001)(189998001)(47776003)(48376002)(5003940100001)(49486002)(229853001)(105606002)(1096002)(4001430100002)(50986999)(87936001)(6806005)(19580395003)(36756003)(104016004)(33646002)(50466002)(2906002)(85426001)(19580405001)(3470700001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR02MB0929;H:ezex10.ezchip.com;FPR:;SPF:Fail;MLV:sfv;MX:1;A:1;LANG:en; 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The rest is now can be seen at ARC srctree: https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/ Now ARC is supporting DT for clockevents and the interrupt controller ARC uses irq domain handling. Compare to last version now clocksource driver do not include clockevent registration since NPS400 can use ARC generic driver. Compare to last version now irqchip driver sets domain as default since it is the root domain. Also mapping of IPI is done in this driver. Last thing is that drivers can be build cleanly for i386 (still runs only for ARC) Note: in order to build we need to merge drivers into srctree which includes new header: soc/nps/common.h This header is part of patch set applied to ARC srctree. Regards, Noam Camus Noam Camus (2): clocksource: Add NPS400 timers driver irqchip: add nps Internal and external irqchips .../interrupt-controller/ezchip,nps400-ic.txt | 17 +++ .../bindings/timer/ezchip,nps400-timer.txt | 15 ++ drivers/clocksource/Kconfig | 7 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 84 +++++++++++ drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-eznps.c | 151 ++++++++++++++++++++ 8 files changed, 282 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c