From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756848AbcBIPBb (ORCPT ); Tue, 9 Feb 2016 10:01:31 -0500 Received: from mail-wm0-f48.google.com ([74.125.82.48]:38561 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755760AbcBIO7l (ORCPT ); Tue, 9 Feb 2016 09:59:41 -0500 From: Krzysztof Adamski X-Google-Original-From: Krzysztof Adamski To: Linus Walleij , Maxime Ripard , Chen-Yu Tsai , Hans de Goede , Lee Jones , Rob Herring , Jens Kuske , Fabian Frederick , Vishnu Patekar , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Krzysztof Adamski Subject: [PATCH v4 2/5] dts: sun8i-h3: Add APB0 related clocks and resets Date: Tue, 9 Feb 2016 15:58:46 +0100 Message-Id: <1455029929-18547-3-git-send-email-k@japko.eu> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455029929-18547-1-git-send-email-k@japko.eu> References: <1455029929-18547-1-git-send-email-k@japko.eu> X-DomainID: tieto.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org APB0 is bearly mentioned in H3 User Manual and it is only setup in the Allwinners kernel dump for CIR. I have verified experimentally that the gate for R_PIO exists and works, though. There are probably other gates there but I don't know their order right now and I don't have access to their peripherals on my board to test them. After some experiments and reviewing how this is organized on other sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO and they are working properly without doing anything so I assume they are connected straight to the 24Mhz oscillator for now. Signed-off-by: Krzysztof Adamski --- arch/arm/boot/dts/sun8i-h3.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 6f6b4e4..a7b2c53 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -285,6 +285,24 @@ clocks = <&osc24M>, <&pll6x2>, <&pll5>; clock-output-names = "mbus"; }; + + apb0: apb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "apb0"; + }; + + apb0_gates: clk@01f01428 { + compatible = "allwinner,sun8i-h3-apb0-gates-clk"; + reg = <0x01f01428 0x4>; + #clock-cells = <1>; + clocks = <&apb0>; + clock-indices = <0>, <1>; + clock-output-names = "apb0_pio", "apb0_ir"; + }; }; soc { @@ -502,5 +520,11 @@ interrupts = , ; }; + + apb0_reset: reset@01f014b0 { + reg = <0x01f014b0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; }; }; -- 2.1.4