From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751720AbcBKQ2h (ORCPT ); Thu, 11 Feb 2016 11:28:37 -0500 Received: from mail-bl2nam02on0055.outbound.protection.outlook.com ([104.47.38.55]:51712 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751334AbcBKQ22 (ORCPT ); Thu, 11 Feb 2016 11:28:28 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; york.ac.uk; dkim=none (message not signed) header.d=none;york.ac.uk; dmarc=bestguesspass action=none header.from=xilinx.com; From: Bharat Kumar Gogada To: , , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH V4 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node. Date: Thu, 11 Feb 2016 21:58:10 +0530 Message-ID: <1455208091-15556-5-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1455208091-15556-1-git-send-email-bharatku@xilinx.com> References: <1455208091-15556-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22124.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(4001430100002)(106466001)(5008740100001)(4326007)(76176999)(87936001)(229853001)(86362001)(6806005)(1096002)(50226001)(52956003)(33646002)(45336002)(5003940100001)(90966002)(63266004)(42186005)(11100500001)(36756003)(586003)(2201001)(5001960100002)(50466002)(103686003)(107886002)(19580405001)(189998001)(2906002)(1220700001)(19580395003)(5001770100001)(36386004)(92566002)(48376002)(46386002)(2950100001)(47776003)(50986999)(107986001)(921003)(1121003)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT156;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: e0029f60-a247-4b6a-4bc9-08d333005df2 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT156; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13018025)(13015025)(13017025)(5005006)(8121501046)(13023025)(13024025)(10201501046)(3002001);SRVR:BL2NAM02HT156;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT156; X-Forefront-PRVS: 08497C3D99 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2016 16:28:25.5892 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT156 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Updated Zynq PCI binding documentation with Microblaze node. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri Acked-by: Rob Herring --- Changes: Adding Microblaze device tree node Documnetation. --- .../devicetree/bindings/pci/xilinx-pcie.txt | 32 ++++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt index 02f979a..ad7c7bf 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -17,7 +17,7 @@ Required properties: Please refer to the standard PCI bus binding document for a more detailed explanation -Optional properties: +Optional properties for Zynq/Microblaze: - bus-range: PCI bus numbers covered Interrupt controller child node @@ -38,13 +38,13 @@ the four INTx interrupts in ISR and route them to this domain. Example: ++++++++ - +Zynq: pci_express: axi-pcie@50000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x10000000 >; + reg = < 0x50000000 0x1000000 >; device_type = "pci"; interrupts = < 0 52 4 >; interrupt-map-mask = <0 0 0 7>; @@ -60,3 +60,29 @@ Example: #interrupt-cells = <1>; }; }; + + +Microblaze: + pci_express: axi-pcie@10000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x10000000 0x4000000>; + device_type = "pci"; + interrupt-parent = <µbalze_0_intc>; + interrupts = <1 2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + }; -- 2.1.1