From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756187AbcBPVWa (ORCPT ); Tue, 16 Feb 2016 16:22:30 -0500 Received: from gabe.freedesktop.org ([131.252.210.177]:48995 "EHLO gabe.freedesktop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755266AbcBPVU0 (ORCPT ); Tue, 16 Feb 2016 16:20:26 -0500 From: Eric Anholt To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, David Airlie , Eric Anholt Subject: [PATCH 5/6] drm/vc4: Fix setting of vertical timings in the CRTC. Date: Tue, 16 Feb 2016 13:20:18 -0800 Message-Id: <1455657619-12030-6-git-send-email-eric@anholt.net> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1455657619-12030-1-git-send-email-eric@anholt.net> References: <1455657619-12030-1-git-send-email-eric@anholt.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It looks like when I went to add the interlaced bits, I just took the existing PV_VERT* block and indented it, instead of copy and pasting it first. Without this, changing resolution never worked. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 5daa824..89562904 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) PV_HORZB_HFP) | VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE)); + CRTC_WRITE(PV_VERTA, + VC4_SET_FIELD(mode->vtotal - mode->vsync_end, + PV_VERTA_VBP) | + VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, + PV_VERTA_VSYNC)); + CRTC_WRITE(PV_VERTB, + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, + PV_VERTB_VFP) | + VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); + if (interlace) { CRTC_WRITE(PV_VERTA_EVEN, VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1, -- 2.7.0