From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932987AbcBXIsF (ORCPT ); Wed, 24 Feb 2016 03:48:05 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47363 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932649AbcBXIsB (ORCPT ); Wed, 24 Feb 2016 03:48:01 -0500 From: Jiri Olsa To: Arnaldo Carvalho de Melo Cc: lkml , David Ahern , Ingo Molnar , Namhyung Kim , Peter Zijlstra , Stephane Eranian , Andi Kleen Subject: [PATCH 14/15] perf x86 intel: Add DATALA events into sysfs Date: Wed, 24 Feb 2016 09:46:55 +0100 Message-Id: <1456303616-26926-15-git-send-email-jolsa@kernel.org> In-Reply-To: <1456303616-26926-1-git-send-email-jolsa@kernel.org> References: <1456303616-26926-1-git-send-email-jolsa@kernel.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding DATALA events into Haaswell events sysfs directory, so it's easier to use them. Adding all DATALA events as specified by Intel SDM manual 18.10.3 PEBS Data Address Profiling. Link: http://lkml.kernel.org/n/tip-dvpk5ys80v41oh5xgqvloviw@git.kernel.org Signed-off-by: Jiri Olsa --- arch/x86/events/intel/core.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a7ec685657a5..199f645aedc1 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3253,6 +3253,26 @@ static __init void intel_ht_bug(void) EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") +EVENT_ATTR_STR(mem-stlb-miss-loads, hsw_stlb_miss_loads, "event=0xd0,umask=0x11"); +EVENT_ATTR_STR(mem-stlb-miss-stores, hsw_stlb_miss_stores, "event=0xd0,umask=0x12"); +EVENT_ATTR_STR(mem-lock-loads, hsw_lock_loads, "event=0xd0,umask=0x21"); +EVENT_ATTR_STR(mem-split-loads, hsw_split_loads, "event=0xd0,umask=0x41"); +EVENT_ATTR_STR(mem-split-stores, hsw_split_stores, "event=0xd0,umask=0x42"); +EVENT_ATTR_STR(mem-all-loads, hsw_all_loads, "event=0xd0,umask=0x81"); +EVENT_ATTR_STR(mem-all-stores, hsw_all_stores, "event=0xd0,umask=0x82"); +EVENT_ATTR_STR(mem-load-l1-hit, hsw_load_l1_hit, "event=0xd1,umask=0x01"); +EVENT_ATTR_STR(mem-load-l2-hit, hsw_load_l2_hit, "event=0xd1,umask=0x02"); +EVENT_ATTR_STR(mem-load-l3-hit, hsw_load_l3_hit, "event=0xd1,umask=0x04"); +EVENT_ATTR_STR(mem-load-l1-miss, hsw_load_l1_miss, "event=0xd1,umask=0x08"); +EVENT_ATTR_STR(mem-load-l2-miss, hsw_load_l2_miss, "event=0xd1,umask=0x10"); +EVENT_ATTR_STR(mem-load-l3-miss, hsw_load_l3_miss, "event=0xd1,umask=0x20"); +EVENT_ATTR_STR(mem-load-hit-lfb, hsw_load_hit_lfb, "event=0xd1,umask=0x40"); +EVENT_ATTR_STR(mem-snp-miss, hsw_snp_miss, "event=0xd2,umask=0x01"); +EVENT_ATTR_STR(mem-snp-hit, hsw_snp_hit, "event=0xd2,umask=0x02"); +EVENT_ATTR_STR(mem-snp-hitm, hsw_snp_hitm, "event=0xd2,umask=0x04"); +EVENT_ATTR_STR(mem-snp-none, hsw_snp_none, "event=0xd2,umask=0x08"); +EVENT_ATTR_STR(mem-local-dram, hsw_local_dram, "event=0xd3,umask=0x01"); + /* Haswell special events */ EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); @@ -3282,6 +3302,25 @@ static struct attribute *hsw_events_attrs[] = { EVENT_PTR(cycles_ct), EVENT_PTR(mem_ld_hsw), EVENT_PTR(mem_st_hsw), + EVENT_PTR(hsw_stlb_miss_loads), + EVENT_PTR(hsw_stlb_miss_stores), + EVENT_PTR(hsw_lock_loads), + EVENT_PTR(hsw_split_loads), + EVENT_PTR(hsw_split_stores), + EVENT_PTR(hsw_all_loads), + EVENT_PTR(hsw_all_stores), + EVENT_PTR(hsw_load_l1_hit), + EVENT_PTR(hsw_load_l2_hit), + EVENT_PTR(hsw_load_l3_hit), + EVENT_PTR(hsw_load_l1_miss), + EVENT_PTR(hsw_load_l2_miss), + EVENT_PTR(hsw_load_l3_miss), + EVENT_PTR(hsw_load_hit_lfb), + EVENT_PTR(hsw_snp_miss), + EVENT_PTR(hsw_snp_hit), + EVENT_PTR(hsw_snp_hitm), + EVENT_PTR(hsw_snp_none), + EVENT_PTR(hsw_local_dram), NULL }; -- 2.4.3