From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752817AbcCGNCn (ORCPT ); Mon, 7 Mar 2016 08:02:43 -0500 Received: from mail.skyhub.de ([78.46.96.112]:60593 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752401AbcCGNCf (ORCPT ); Mon, 7 Mar 2016 08:02:35 -0500 From: Borislav Petkov To: Ingo Molnar Cc: X86 ML , linux-edac , LKML Subject: [PATCH 0/5] x86/RAS: Enable error decoding of AMD Scalable MCA errors Date: Mon, 7 Mar 2016 14:02:16 +0100 Message-Id: <1457355741-32651-1-git-send-email-bp@alien8.de> X-Mailer: git-send-email 2.3.5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Borislav Petkov Hi, this adds support for the upcoming AMD Scalable MCA error decoding scheme to Linux (F17h stuff) (patch 2). The rest is cleanups and clarifications. Patches ontop of tip/ras/core. Aravind Gopalakrishnan (5): x86/mce: Move MCx_CONFIG MSR definitions x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors x86/mce/AMD: Fix logic to obtain block address x86/mce: Clarify comments regarding deferred error x86/mce/AMD: Document some functionality arch/x86/include/asm/amd_nb.h | 26 ++- arch/x86/include/asm/mce.h | 69 +++++++- arch/x86/include/asm/msr-index.h | 4 - arch/x86/kernel/cpu/mcheck/mce_amd.c | 120 +++++++++---- drivers/edac/mce_amd.c | 335 ++++++++++++++++++++++++++++++++++- 5 files changed, 503 insertions(+), 51 deletions(-) -- 2.3.5