From: Borislav Petkov <bp@alien8.de>
To: Ingo Molnar <mingo@kernel.org>
Cc: X86 ML <x86@kernel.org>, linux-edac <linux-edac@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/5] x86/mce: Move MCx_CONFIG MSR definitions
Date: Mon, 7 Mar 2016 14:02:17 +0100 [thread overview]
Message-ID: <1457355741-32651-2-git-send-email-bp@alien8.de> (raw)
In-Reply-To: <1457355741-32651-1-git-send-email-bp@alien8.de>
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Those MSRs are used only by the MCE code so move them there.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1456785179-14378-2-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/mce.h | 4 ++++
arch/x86/include/asm/msr-index.h | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2ea4527e462f..80ba0a8d6d06 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -91,6 +91,10 @@
#define MCE_LOG_LEN 32
#define MCE_LOG_SIGNATURE "MACHINECHECK"
+/* AMD Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
+#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
+
/*
* This structure contains all data related to the MCE log. Also
* carries a signature to make it easier to find from external
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 552346598dab..b05402ef3b84 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -264,10 +264,6 @@
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
-/* 'SMCA': AMD64 Scalable MCA */
-#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
-#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
-
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
--
2.3.5
next prev parent reply other threads:[~2016-03-07 13:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 13:02 [PATCH 0/5] x86/RAS: Enable error decoding of AMD Scalable MCA errors Borislav Petkov
2016-03-07 13:02 ` Borislav Petkov [this message]
2016-03-07 13:02 ` [PATCH 2/5] x86/mce/AMD, EDAC: Enable error decoding of " Borislav Petkov
2016-03-07 13:02 ` [PATCH 3/5] x86/mce/AMD: Fix logic to obtain block address Borislav Petkov
2016-03-07 13:02 ` [PATCH 4/5] x86/mce: Clarify comments regarding deferred error Borislav Petkov
2016-03-07 13:02 ` [PATCH 5/5] x86/mce/AMD: Document some functionality Borislav Petkov
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