From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934312AbcCOHjF (ORCPT ); Tue, 15 Mar 2016 03:39:05 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:53154 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934279AbcCOHiV (ORCPT ); Tue, 15 Mar 2016 03:38:21 -0400 X-AuditID: cbfee68f-f793a6d000001364-96-56e7bbe46c85 From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock Date: Tue, 15 Mar 2016 16:38:04 +0900 Message-id: <1458027490-13787-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> References: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsWyRsSkSPfJ7udhBqveqllsP/KM1eL6l+es FvOPnGO1mHR/AovFjV9trBavXxha9D9+zWyx6fE1VovLu+awWcw4v4/JYtHWL+wWh9+0s1rM mPySzWLVrj+MDnweO2fdZffYtKqTzWPzknqPvi2rGD0+b5ILYI3isklJzcksSy3St0vgyph2 4yVjwXaZiiWXj7A2MN4W72Lk5JAQMJFY1j2PEcIWk7hwbz1bFyMXh5DACkaJiddvMMIU3dmz nhXEFhJYyijR+SkIougLo8SjztdgCTYBLYn9L26wgdgiAnESEy9C2MwCs5gk5s0vBLGFBRwl vj/9xwRiswioSpyZvhSshlfAVeL2ojMsEMvkJD7secQOYnMKuEmcvnqfEWKxq8S5FetYQBZL CJxil1i3+TErxCABiW+TDwElOIASshKbDjBDzJGUOLjiBssERuEFjAyrGEVTC5ILipPSi4z1 ihNzi0vz0vWS83M3MQIj5fS/Z/07GO8esD7EKMDBqMTDO0PqeZgQa2JZcWXuIUZToA0TmaVE k/OB8ZhXEm9obGZkYWpiamxkbmmmJM67UOpnsJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQbG tvbEuokPzbedttrIref1uSu4QmNzCufORv9r7VevnXHm6mzpXV4XEf3uzKrK5Fj5l0IuB5kv 2J6Y2n7xvOfEGddKo0q+L1gzwdZ09tr7HL49sw4feLl8vn6HzN5Fi8znXE7kyXFYfPAbx+7H Ca7Hf/OyXOJjlD0+KaXmWrKqYZlBQ/SHCtY1SizFGYmGWsxFxYkAwxFh9o8CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJIsWRmVeSWpSXmKPExsVy+t9jAd0nu5+HGbxtU7DYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjFj2o2XjAXbZSqWXD7C2sB4W7yLkZNDQsBE4s6e9awQtpjE hXvr2UBsIYGljBKdn4K6GLmA7C+MEo86X4MVsQloSex/cQOsSEQgTmLiRQibWWAWk8S8+YUg trCAo8T3p/+YQGwWAVWJM9OXgtXwCrhK3F50hgVimZzEhz2P2EFsTgE3idNX7zNCLHaVOLdi HcsERt4FjAyrGCVSC5ILipPScw3zUsv1ihNzi0vz0vWS83M3MYKj8ZnUDsaDu9wPMQpwMCrx 8H6QeR4mxJpYVlyZe4hRgoNZSYTXbRdQiDclsbIqtSg/vqg0J7X4EKMp0GETmaVEk/OBiSKv JN7Q2MTMyNLI3NDCyNhcSZz38f91YUIC6YklqdmpqQWpRTB9TBycUg2MjqKzHj8+Yqt/iGVP 3IEFh4rEJ5ZuZUxe5nfK+Zyhflh+7K+Lq3l5b4t0/zRku/lm8snlJmt5fq3+HSB7ZbKR+Lva hd+atQ5zWyyN11LwlFeMDJsnrX7jUOM01/oLSXOM5zS9SE7Pu8H9v5NxTvvsg/cebNAVcVxo +/jPXoY04XuS6q/Lj+u4K7EUZyQaajEXFScCALsmpJvcAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pankaj Dubey This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Pankaj Dubey Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 6 ++++++ include/dt-bindings/clock/exynos3250.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index fdd41b17a24f..bc60e399d1bc 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), /* DIV_PERIL0 */ + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..ddb874130d86 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,7 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +128,7 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +225,7 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +252,13 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 249 /* * CMU DMC -- 1.9.1