From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964868AbcCOHiv (ORCPT ); Tue, 15 Mar 2016 03:38:51 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:49974 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934247AbcCOHiQ (ORCPT ); Tue, 15 Mar 2016 03:38:16 -0400 X-AuditID: cbfee68f-f793a6d000001364-99-56e7bbe49911 From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock Date: Tue, 15 Mar 2016 16:38:05 +0900 Message-id: <1458027490-13787-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> References: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsWyRsSkSPfJ7udhBktP2VhsP/KM1eL6l+es FvOPnGO1mHR/AovFjV9trBavXxha9D9+zWyx6fE1VovLu+awWcw4v4/JYtHWL+wWh9+0s1rM mPySzWLVrj+MDnweO2fdZffYtKqTzWPzknqPvi2rGD0+b5ILYI3isklJzcksSy3St0vgyvh9 ZBZjwQ7Zigk7d7A2MB6X6GLk5JAQMJHY+/c+C4QtJnHh3nq2LkYuDiGBFYwSm2Y9Zocp6nnx mBEisZRRouHwOhYI5wujxKPO16wgVWwCWhL7X9xgA7FFBOIkJl6EsJkFZjFJzJtfCGILCzhI rG1ZygRiswioSszYNJkRxOYVcJVo2nqAEWKbnMSHPY/ANnMKuEmcvnofLC4EVHNuBcRiCYFT 7BI7G/azQgwSkPg2+RBQggMoISux6QAzxBxJiYMrbrBMYBRewMiwilE0tSC5oDgpvchYrzgx t7g0L10vOT93EyMwVk7/e9a/g/HuAetDjAIcjEo8vDOknocJsSaWFVfmHmI0BdowkVlKNDkf GJF5JfGGxmZGFqYmpsZG5pZmSuK8C6V+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpgNF48 Mz0q/FOD3h9h9Utry85O2Rndwnhl2aN4p62f5fZFM5msVfLyO/RRX4glmbM93sDxmPDdPnat DbdjZ0f3J8i53WLYYmnAqr1/odGPXzLe/pL3Vm/S8zZ+saE8zEcr6ueP97vPp65KN0wS2LJX 96T9Q/btpwS8/B4rC2725z3B18nQF1igxFKckWioxVxUnAgA/0L5hZACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsVy+t9jAd0nu5+HGcxqMrPYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjHj95FZjAU7ZCsm7NzB2sB4XKKLkZNDQsBEoufFY0YIW0zi wr31bF2MXBxCAksZJRoOr2OBcL4wSjzqfM0KUsUmoCWx/8UNNhBbRCBOYuJFCJtZYBaTxLz5 hSC2sICDxNqWpUwgNouAqsSMTZPBNvAKuEo0bT0AtU1O4sOeR+wgNqeAm8Tpq/fB4kJANedW rGOZwMi7gJFhFaNEakFyQXFSeq5hXmq5XnFibnFpXrpecn7uJkZwPD6T2sF4cJf7IUYBDkYl Ht4PMs/DhFgTy4orcw8xSnAwK4nwuu0CCvGmJFZWpRblxxeV5qQWH2I0BTpsIrOUaHI+MFXk lcQbGpuYGVkamRtaGBmbK4nzPv6/LkxIID2xJDU7NbUgtQimj4mDU6qBkbvl0omXDb2fzlke YWaMKtzv3tEw0Vsz6e030UfHGTxKL070WqjMnXc21W1jlmZEZq2947V1bW+3+4T1br6ZYlNw 7cfv67oZzlJ8B43KBKMFH2+x81vlNat4u++0PwfXG17s4WJ3vjbLJNS9eu3K9ednsvu0pM6N 1o/xi7xs3PNZNGeZl9QuJZbijERDLeai4kQAINbgp90CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ include/dt-bindings/clock/exynos3250.h | 7 ++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index bc60e399d1bc..16575ee874cb 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index ddb874130d86..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -80,6 +80,7 @@ #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -129,6 +130,8 @@ #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -226,6 +229,7 @@ #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 #define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -253,12 +257,13 @@ #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 #define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 249 +#define CLK_NR_CLKS 250 /* * CMU DMC -- 1.9.1