From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752457AbcCVSJg (ORCPT ); Tue, 22 Mar 2016 14:09:36 -0400 Received: from mga03.intel.com ([134.134.136.65]:35257 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750901AbcCVSJe (ORCPT ); Tue, 22 Mar 2016 14:09:34 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,378,1455004800"; d="scan'208";a="916615265" From: Andi Kleen To: acme@kernel.org Cc: jolsa@kernel.org, peterz@infradead.org, linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 2/2] perf, tools: Fix documentation of :ppp in perf list Date: Tue, 22 Mar 2016 11:09:31 -0700 Message-Id: <1458670171-16782-2-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1458670171-16782-1-git-send-email-andi@firstfloor.org> References: <1458670171-16782-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen Correctly document what is implemented for :ppp on Intel CPUs in recent kernels. Acked-by: Jiri Olsa Signed-off-by: Andi Kleen --- tools/perf/Documentation/perf-list.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index 0059905..cc87111 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid - 3 - SAMPLE_IP must have 0 skid + 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid + sample shadowing effects. For Intel systems precise event sampling is implemented with PEBS -which supports up to precise-level 2. +which supports up to precise-level 2, and precise level 3 for +some special cases On AMD systems it is implemented using IBS (up to precise-level 2). The precise modifier works with event types 0x76 (cpu-cycles, CPU -- 2.5.5