From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964799AbcDTJ6f (ORCPT ); Wed, 20 Apr 2016 05:58:35 -0400 Received: from mail-bn1on0095.outbound.protection.outlook.com ([157.56.110.95]:47328 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S964786AbcDTJ6b (ORCPT ); Wed, 20 Apr 2016 05:58:31 -0400 X-Greylist: delayed 972 seconds by postgrey-1.27 at vger.kernel.org; Wed, 20 Apr 2016 05:58:30 EDT Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , Subject: [RESEND PATCH 8/8] clk: imx7d: only enable minimum required clocks Date: Wed, 20 Apr 2016 17:34:40 +0800 Message-ID: <1461144880-8724-9-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461144880-8724-1-git-send-email-aisheng.dong@nxp.com> References: <1461144880-8724-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131056189475488082;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(4326007)(50466002)(2950100001)(11100500001)(19580405001)(104016004)(19580395003)(50986999)(5008740100001)(6806005)(76176999)(586003)(1220700001)(1096002)(36756003)(86362001)(48376002)(87936001)(77096005)(110136002)(105606002)(189998001)(33646002)(50226001)(106466001)(5003940100001)(92566002)(229853001)(81166005)(2351001)(85426001)(2906002)(7059030)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BY2PR0301MB0709;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:sfv;A:1;MX:1;LANG:en; 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Therefore we enabled all clocks by default in clock driver initialization for other module clocks operate well. After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ON', clk core can handle such clock type well, so we don't have to enable them all by default anymore. Instead, we only enable a minimum required set of clocks. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-imx7d.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 980b2b8..18d23da 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -361,6 +361,14 @@ static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; +static int const clks_init_on[] __initconst = { + IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK, + IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, + IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, + IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, + IMX7D_AHB_CHANNEL_ROOT_CLK, +}; + static struct clk_onecell_data clk_data; static struct clk ** const uart_clks[] __initconst = { @@ -846,14 +854,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - /* TO BE FIXED LATER - * Enable all clock to bring up imx7, otherwise system will be halt and block - * the other part upstream Because imx7d clock design changed, clock framework - * need do a little modify. - * Dong Aisheng is working on this. After that, this part need be changed. - */ - for (i = 0; i < IMX7D_CLK_END; i++) - clk_prepare_enable(clks[i]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); -- 1.9.1