From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754007AbcDYIFr (ORCPT ); Mon, 25 Apr 2016 04:05:47 -0400 Received: from mga03.intel.com ([134.134.136.65]:3336 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753876AbcDYIFn (ORCPT ); Mon, 25 Apr 2016 04:05:43 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,532,1455004800"; d="scan'208";a="791732355" From: Lu Baolu To: felipe.balbi@linux.intel.com, Mathias Nyman , Greg Kroah-Hartman , Lee Jones , Heikki Krogerus , MyungJoo Ham , Chanwoo Choi , Liam Girdwood , Mark Brown Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v6 09/10] usb: pci-quirks: add Intel USB drcfg mux device Date: Mon, 25 Apr 2016 16:04:55 +0800 Message-Id: <1461571496-9600-10-git-send-email-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1461571496-9600-1-git-send-email-baolu.lu@linux.intel.com> References: <1461571496-9600-1-git-send-email-baolu.lu@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In some Intel platforms, a single usb port is shared between USB host and device controllers. The shared port is under control of a switch which is defined in the Intel vendor defined extended capability for xHCI. This patch adds the support to detect and create the platform device for the port mux switch. Signed-off-by: Lu Baolu Reviewed-by: Felipe Balbi --- drivers/usb/host/pci-quirks.c | 45 ++++++++++++++++++++++++++++++++++++++-- drivers/usb/host/xhci-ext-caps.h | 2 ++ 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 35af362..9bb7aa1 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -16,10 +16,11 @@ #include #include #include +#include + #include "pci-quirks.h" #include "xhci-ext-caps.h" - #define UHCI_USBLEGSUP 0xc0 /* legacy support */ #define UHCI_USBCMD 0 /* command register */ #define UHCI_USBINTR 4 /* interrupt register */ @@ -78,6 +79,8 @@ #define USB_INTEL_USB3_PSSEN 0xD8 #define USB_INTEL_USB3PRM 0xDC +#define DEVICE_ID_INTEL_BROXTON_P_XHCI 0x5aa8 + /* * amd_chipset_gen values represent AMD different chipset generations */ @@ -956,6 +959,41 @@ void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) } EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); +static void create_intel_usb_mux_device(struct pci_dev *xhci_pdev, + void __iomem *base) +{ + struct platform_device *plat_dev; + struct property_set pset; + int ret; + + struct property_entry pentry[] = { + PROPERTY_ENTRY_U64("reg-start", + pci_resource_start(xhci_pdev, 0) + 0x80d8), + PROPERTY_ENTRY_U64("reg-size", 8), + { }, + }; + + if (!xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_USB_MUX)) + return; + + plat_dev = platform_device_alloc("intel-mux-drcfg", + PLATFORM_DEVID_NONE); + if (!plat_dev) + return; + + plat_dev->dev.parent = &xhci_pdev->dev; + pset.properties = pentry; + platform_device_add_properties(plat_dev, &pset); + + ret = platform_device_add(plat_dev); + if (ret) { + dev_warn(&xhci_pdev->dev, + "failed to create mux device with error %d", + ret); + platform_device_put(plat_dev); + } +} + /** * PCI Quirks for xHCI. * @@ -1022,8 +1060,11 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev) writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); hc_init: - if (pdev->vendor == PCI_VENDOR_ID_INTEL) + if (pdev->vendor == PCI_VENDOR_ID_INTEL) { usb_enable_intel_xhci_ports(pdev); + if (pdev->device == DEVICE_ID_INTEL_BROXTON_P_XHCI) + create_intel_usb_mux_device(pdev, base); + } op_reg_base = base + XHCI_HC_LENGTH(readl(base)); diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h index e0244fb..e368ccb 100644 --- a/drivers/usb/host/xhci-ext-caps.h +++ b/drivers/usb/host/xhci-ext-caps.h @@ -51,6 +51,8 @@ #define XHCI_EXT_CAPS_ROUTE 5 /* IDs 6-9 reserved */ #define XHCI_EXT_CAPS_DEBUG 10 +/* Vendor defined 192-255 */ +#define XHCI_EXT_CAPS_INTEL_USB_MUX 192 /* USB Legacy Support Capability - section 7.1.1 */ #define XHCI_HC_BIOS_OWNED (1 << 16) #define XHCI_HC_OS_OWNED (1 << 24) -- 2.1.4