From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752684AbcD1Pg2 (ORCPT ); Thu, 28 Apr 2016 11:36:28 -0400 Received: from mga09.intel.com ([134.134.136.24]:25483 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751539AbcD1Pg1 (ORCPT ); Thu, 28 Apr 2016 11:36:27 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,547,1455004800"; d="scan'208";a="942192767" From: Alexander Shishkin To: Peter Zijlstra Cc: Thomas Gleixner , x86@kernel.org, Borislav Petkov , Ingo Molnar , linux-kernel@vger.kernel.org, vince@deater.net, eranian@google.com, Arnaldo Carvalho de Melo , Mathieu Poirier , Alexander Shishkin Subject: [PATCH v0 3/3] perf, x86: Bypass PT vs LBR exclusivity if the core supports it Date: Thu, 28 Apr 2016 18:35:46 +0300 Message-Id: <1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461857746-31346-1-git-send-email-alexander.shishkin@linux.intel.com> References: <1461857746-31346-1-git-send-email-alexander.shishkin@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Not all cores prevent using Intel PT and LBRs simultaneously, although most of them still do as of today. This patch adds an opt-in flag for such cores to disable mutual exclusivity between PT and LBR; also flip it on for Goldmont. Signed-off-by: Alexander Shishkin --- arch/x86/events/core.c | 6 ++++++ arch/x86/events/intel/core.c | 1 + arch/x86/events/perf_event.h | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 41d93d0e97..5e5e76a52f 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -360,6 +360,9 @@ int x86_add_exclusive(unsigned int what) { int i; + if (x86_pmu.lbr_pt_coexist) + return 0; + if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { mutex_lock(&pmc_reserve_mutex); for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { @@ -380,6 +383,9 @@ fail_unlock: void x86_del_exclusive(unsigned int what) { + if (x86_pmu.lbr_pt_coexist) + return; + atomic_dec(&x86_pmu.lbr_exclusive[what]); atomic_dec(&active_events); } diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 79b59437f5..e36422c687 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3609,6 +3609,7 @@ __init int intel_pmu_init(void) */ x86_pmu.pebs_aliases = NULL; x86_pmu.pebs_prec_dist = true; + x86_pmu.lbr_pt_coexist = true; x86_pmu.flags |= PMU_FL_HAS_RSP_1; pr_cont("Goldmont events, "); break; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 7d62a02f49..8bd764df81 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -601,6 +601,7 @@ struct x86_pmu { u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ + bool lbr_pt_coexist; /* LBR may coexist with PT */ /* * Intel PT/LBR/BTS are exclusive -- 2.8.0.rc3