From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934248AbcECROe (ORCPT ); Tue, 3 May 2016 13:14:34 -0400 Received: from plaes.org ([188.166.43.21]:38298 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934213AbcECROc (ORCPT ); Tue, 3 May 2016 13:14:32 -0400 From: Priit Laes To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Maxime Ripard , Chen-Yu Tsai Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Priit Laes Subject: [PATCH 2/2] ARM: sun7i: dt: Add pll3 and pll7 clocks Date: Tue, 3 May 2016 20:14:19 +0300 Message-Id: <1462295659-6945-3-git-send-email-plaes@plaes.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462295659-6945-1-git-send-email-plaes@plaes.org> References: <1462295659-6945-1-git-send-email-plaes@plaes.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable pll3 and pll7 clocks that are needed by display clocks. --- arch/arm/boot/dts/sun7i-a20.dtsi | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bf5d056..2688512 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -187,6 +187,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -211,6 +220,22 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clock = <&osc3M>; + clock-output-names = "pll3"; +}; + + pll3x2: pll3x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; @@ -236,6 +261,22 @@ "pll6_div_4"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clock = <&osc3M>; + clock-output-names = "pll7"; +}; + + pll7x2: pll7x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll7-2x"; + }; + pll8: clk@01c20040 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; -- 2.8.1