From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757633AbcEEPgA (ORCPT ); Thu, 5 May 2016 11:36:00 -0400 Received: from mail-bn1bon0087.outbound.protection.outlook.com ([157.56.111.87]:33329 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756568AbcEEPf5 (ORCPT ); Thu, 5 May 2016 11:35:57 -0400 X-Greylist: delayed 80366 seconds by postgrey-1.27 at vger.kernel.org; Thu, 05 May 2016 11:35:57 EDT Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=nxp.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; From: =?UTF-8?q?Horia=20Geant=C4=83?= To: Arnd Bergmann CC: , Subject: [PATCH v2 1/8] asm-generic/io.h: allow barriers in io{read,write}{16,32}be Date: Thu, 5 May 2016 18:35:45 +0300 Message-ID: <1462462545-27637-1-git-send-email-horia.geanta@nxp.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1462462435-27403-1-git-send-email-horia.geanta@nxp.com> References: <1462462435-27403-1-git-send-email-horia.geanta@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; 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I think the only affected architecture is ARC, since ARM and ARM64 both override the big-endian accessors to have the correct barriers, and all others don't use barriers at all." -suggests a fix for the same problem in existing code (16/32-bit accessors); the fix leads "to a double-swap on architectures that don't override the io{read,write}{16,32}be accessors, but it will work correctly on all architectures without them having to override these accessors." Suggested-by: Arnd Bergmann Signed-off-by: Horia Geantă --- include/asm-generic/io.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index eed3bbe88c8a..b79fb2c248a1 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -613,7 +613,7 @@ static inline void iowrite32(u32 value, volatile void __iomem *addr) #define ioread16be ioread16be static inline u16 ioread16be(const volatile void __iomem *addr) { - return __be16_to_cpu(__raw_readw(addr)); + return swab16(readw(addr)); } #endif @@ -621,7 +621,7 @@ static inline u16 ioread16be(const volatile void __iomem *addr) #define ioread32be ioread32be static inline u32 ioread32be(const volatile void __iomem *addr) { - return __be32_to_cpu(__raw_readl(addr)); + return swab32(readl(addr)); } #endif @@ -629,7 +629,7 @@ static inline u32 ioread32be(const volatile void __iomem *addr) #define iowrite16be iowrite16be static inline void iowrite16be(u16 value, void volatile __iomem *addr) { - __raw_writew(__cpu_to_be16(value), addr); + writew(swab16(value), addr); } #endif @@ -637,7 +637,7 @@ static inline void iowrite16be(u16 value, void volatile __iomem *addr) #define iowrite32be iowrite32be static inline void iowrite32be(u32 value, volatile void __iomem *addr) { - __raw_writel(__cpu_to_be32(value), addr); + writel(swab32(value), addr); } #endif -- 2.4.4