From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757437AbcEEQcL (ORCPT ); Thu, 5 May 2016 12:32:11 -0400 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:10525 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754725AbcEEQcJ (ORCPT ); Thu, 5 May 2016 12:32:09 -0400 X-IronPort-AV: E=Sophos;i="5.24,582,1455004800"; d="scan'208";a="94266866" From: Ray Jui To: Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, Ray Jui , Alex Barba Subject: [PATCH v3] Workaround for Broadcom NS2 gicv2m implementation Date: Thu, 5 May 2016 09:32:00 -0700 Message-Id: <1462465921-3220-1-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Alex Barba discovered Broadcom NS2 GICv2m implementation has an erratum where the MSI data needs to be the SPI number subtracted by an offset of 32, for the correct MSI interrupt to be triggered. We are now implementating the workaround based on readings from the MSI_IIDR register. Patch series is developed based on Linux v4.6-rc1 and available at: https://github.com/Broadcom/arm64-linux/tree/gicv2m-iproc-v3 Changes from v2: - Improved the logic of dealing with MSI_IIDR readings by using a switch statement suggested by Marc Zyngier Changes from v1: - Changed from DT based approach to the approch similar to APM that is based on readings from the MSI_IIDR register Ray Jui (1): irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum drivers/irqchip/irq-gic-v2m.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) -- 2.1.4