From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932351AbcEQOcS (ORCPT ); Tue, 17 May 2016 10:32:18 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:39863 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751243AbcEQOcQ (ORCPT ); Tue, 17 May 2016 10:32:16 -0400 From: Paul Burton To: , Ralf Baechle CC: Matt Redfearn , Paul Burton , Marc Zyngier , Jason Cooper , Thomas Gleixner , Subject: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use Date: Tue, 17 May 2016 15:31:06 +0100 Message-ID: <1463495466-29689-4-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1463495466-29689-1-git-send-email-paul.burton@imgtec.com> References: <1463495466-29689-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.141] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When EIC mode is in use (cpu_has_veic is true) enable it on each CPU during GIC initialisation. Otherwise there may be a mismatch between the hardware default interrupt model & that expected by the kernel. Signed-off-by: Paul Burton --- drivers/irqchip/irq-mips-gic.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 4dffccf..bc23c92 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -956,7 +956,7 @@ static void __init __gic_init(unsigned long gic_base_addr, unsigned int cpu_vec, unsigned int irqbase, struct device_node *node) { - unsigned int gicconfig; + unsigned int gicconfig, cpu; unsigned int v[2]; __gic_base_addr = gic_base_addr; @@ -973,6 +973,14 @@ static void __init __gic_init(unsigned long gic_base_addr, gic_vpes = gic_vpes + 1; if (cpu_has_veic) { + /* Set EIC mode for all VPEs */ + for_each_present_cpu(cpu) { + gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), + mips_cm_vp_id(cpu)); + gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL), + GIC_VPE_CTL_EIC_MODE_MSK); + } + /* Always use vector 1 in EIC mode */ gic_cpu_pin = 0; timer_cpu_pin = gic_cpu_pin; -- 2.8.2