From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932464AbcEROqv (ORCPT ); Wed, 18 May 2016 10:46:51 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:52126 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753137AbcEROqt (ORCPT ); Wed, 18 May 2016 10:46:49 -0400 From: Matt Redfearn To: Ralf Baechle CC: Matt Redfearn , , Joshua Kinard , , James Hogan , Chris Packham , "Paul Burton" Subject: [PATCH 1/2] MIPS: Add definitions of SegCtl registers and use them Date: Wed, 18 May 2016 15:45:21 +0100 Message-ID: <1463582722-31420-1-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.116] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by: Matt Redfearn --- arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++--- arch/mips/include/asm/mipsregs.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h index 0cf8622db27f..ab03eb3fadac 100644 --- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h @@ -56,7 +56,7 @@ (0 << MIPS_SEGCFG_PA_SHIFT) | \ (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) or t0, t2 - mtc0 t0, $5, 2 + mtc0 t0, CP0_SEGCTL0 /* SegCtl1 */ li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ @@ -67,7 +67,7 @@ (0 << MIPS_SEGCFG_PA_SHIFT) | \ (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) ins t0, t1, 16, 3 - mtc0 t0, $5, 3 + mtc0 t0, CP0_SEGCTL1 /* SegCtl2 */ li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ @@ -77,7 +77,7 @@ (4 << MIPS_SEGCFG_PA_SHIFT) | \ (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) or t0, t2 - mtc0 t0, $5, 4 + mtc0 t0, CP0_SEGCTL2 jal mips_ihb mfc0 t0, $16, 5 diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3ad19ad04d8a..639137f12f1a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -48,6 +48,9 @@ #define CP0_CONF $3 #define CP0_CONTEXT $4 #define CP0_PAGEMASK $5 +#define CP0_SEGCTL0 $5, 2 +#define CP0_SEGCTL1 $5, 3 +#define CP0_SEGCTL2 $5, 4 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_HWRENA $7, 0 -- 2.5.0