From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423792AbcFMONt (ORCPT ); Mon, 13 Jun 2016 10:13:49 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:33502 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423255AbcFMONs (ORCPT ); Mon, 13 Jun 2016 10:13:48 -0400 From: Alexandre TORGUE To: Russell King , Ezequiel Garcia , , Maxime Coquelin , CC: , Subject: [PATCH] ARM: V7M: Add dsb before jumping in handler mode Date: Mon, 13 Jun 2016 16:12:51 +0200 Message-ID: <1465827171-15847-1-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-06-13_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to ARM AN321 (section 4.12): "If the vector table is in writable memory such as SRAM, either relocated by VTOR or a device dependent memory remapping mechanism, then architecturally a memory barrier instruction is required after the vector table entry is updated, and if the exception is to be activated immediately" Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 7229d8d..2ddc435 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -104,6 +104,7 @@ __v7m_setup: badr r1, 1f ldr r5, [r12, #11 * 4] @ read the SVC vector entry str r1, [r12, #11 * 4] @ write the temporary SVC vector entry + dsb mov r6, lr @ save LR ldr sp, =init_thread_union + THREAD_START_SP cpsie i -- 1.9.1