From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <pbonzini@redhat.com>, <rkrcmar@redhat.com>, <joro@8bytes.org>,
<alex.williamson@redhat.com>
Cc: <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sherry.hurwitz@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PART2 RFC v2 10/10] svm: Update AMD IOMMU IRTE with vcpu scheduling information when enable AVIC
Date: Mon, 13 Jun 2016 17:06:50 -0500 [thread overview]
Message-ID: <1465855611-10092-11-git-send-email-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <1465855611-10092-1-git-send-email-suravee.suthikulpanit@amd.com>
In case AVIC is enabled, during vcpu_load/unload, SVM needs to update
IOMMU IRTE with appropriate host physical APIC ID. Also, when
vcpu_blocking/unblocking, SVM needs to update the is-running bit in
the IOMMU IRTE. Both are achieved via calling amd_iommu_update_ga().
However, if GA mode is not enabled for the pass-through device,
IOMMU driver will simply just return when calling amd_iommu_update_ga.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
arch/x86/kvm/svm.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5a0b89a..803351a 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1384,6 +1384,18 @@ free_avic:
return err;
}
+static inline int
+avic_update_iommu(struct kvm_vcpu *vcpu, int cpu, phys_addr_t pa, bool r)
+{
+ struct kvm_arch *vm_data = &vcpu->kvm->arch;
+
+ if (!kvm_arch_has_assigned_device(vcpu->kvm))
+ return 0;
+
+ return amd_iommu_update_ga(vcpu->vcpu_id, cpu, vm_data->avic_tag,
+ (pa & AVIC_HPA_MASK), r);
+}
+
/**
* This function is called during VCPU halt/unhalt.
*/
@@ -1406,9 +1418,16 @@ static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
WARN_ON(is_run == !!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK));
entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
- if (is_run)
+ if (is_run) {
entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
- WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
+ WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
+ avic_update_iommu(vcpu, h_physical_id,
+ page_to_phys(svm->avic_backing_page), 1);
+ } else {
+ avic_update_iommu(vcpu, h_physical_id,
+ page_to_phys(svm->avic_backing_page), 0);
+ WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
+ }
}
static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
@@ -1435,6 +1454,9 @@ static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
+ avic_update_iommu(vcpu, h_physical_id,
+ page_to_phys(svm->avic_backing_page),
+ svm->avic_is_running);
}
static void avic_vcpu_put(struct kvm_vcpu *vcpu)
@@ -1446,6 +1468,10 @@ static void avic_vcpu_put(struct kvm_vcpu *vcpu)
return;
entry = READ_ONCE(*(svm->avic_physical_id_cache));
+ if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
+ avic_update_iommu(vcpu, -1,
+ page_to_phys(svm->avic_backing_page), 0);
+
entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
}
--
1.9.1
next prev parent reply other threads:[~2016-06-13 22:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-13 22:06 [PART2 RFC v2 00/10] iommu/AMD: Introduce IOMMU AVIC support Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 01/10] iommu/amd: Detect and enable guest vAPIC support Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 02/10] iommu/amd: Add support for 128-bit IRTE Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 03/10] iommu/amd: Detect and initialize guest vAPIC log Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 04/10] iommu/amd: Adding GALOG interrupt handler Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 05/10] iommu/amd: Introduce amd_iommu_update_ga() Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 06/10] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 07/10] iommu/amd: Enable vAPIC interrupt remapping mode by default Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 08/10] svm: Introduce AMD IOMMU avic_ga_log_notifier Suravee Suthikulpanit
2016-06-13 22:06 ` [PART2 RFC v2 09/10] svm: Implements update_pi_irte hook to setup posted interrupt Suravee Suthikulpanit
2016-06-13 22:06 ` Suravee Suthikulpanit [this message]
2016-06-21 13:50 ` [PART2 RFC v2 00/10] iommu/AMD: Introduce IOMMU AVIC support Joerg Roedel
2016-06-21 14:27 ` Suravee Suthikulanit
2016-06-21 14:46 ` Joerg Roedel
2016-06-21 15:45 ` Suravee Suthikulanit
2016-06-21 15:15 ` Paolo Bonzini
2016-07-05 18:51 ` Suravee Suthikulpanit
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