From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754779AbcFQAKq (ORCPT ); Thu, 16 Jun 2016 20:10:46 -0400 Received: from mail-bn1bon0070.outbound.protection.outlook.com ([157.56.111.70]:52148 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754126AbcFQAKo (ORCPT ); Thu, 16 Jun 2016 20:10:44 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=nxp.com;nxp.com; dkim=none (message not signed) header.d=none; From: Li Yang To: Olof Johansson , Arnd Bergmann , Shawn Guo , Rob Herring , Stuart Yoder , , , CC: Li Yang Subject: [PATCH 2/2] arm64: dts: ls2080a: Add cache nodes for cacheinfo support Date: Thu, 16 Jun 2016 18:35:04 -0500 Message-ID: <1466120104-12023-2-git-send-email-leoyang.li@nxp.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1466120104-12023-1-git-send-email-leoyang.li@nxp.com> References: <1466120104-12023-1-git-send-email-leoyang.li@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131105938174459393;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(50986999)(92566002)(5008740100001)(6806005)(356003)(189998001)(104016004)(50466002)(77096005)(76176999)(5001770100001)(97736004)(48376002)(85426001)(2906002)(586003)(86362001)(8676002)(81156014)(81166006)(47776003)(36756003)(8936002)(8666005)(2201001)(50226002)(5003940100001)(19580395003)(2950100001)(87936001)(11100500001)(19580405001)(68736007)(33646002)(229853001)(105606002)(106466001)(4326007)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR03MB2371;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;MX:1;A:1;CAT:NONE;LANG:en;CAT:NONE; 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Signed-off-by: Li Yang --- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 3187c82..0f4b9c1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -67,6 +67,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@1 { @@ -74,6 +75,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@100 { @@ -81,6 +83,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x100>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@101 { @@ -88,6 +91,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x101>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@200 { @@ -95,6 +99,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x200>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@201 { @@ -102,6 +107,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x201>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@300 { @@ -109,6 +115,7 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x300>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; }; cpu@301 { @@ -116,6 +123,23 @@ compatible = "arm,cortex-a57"; reg = <0x0 0x301>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; }; }; -- 1.9.0