From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752635AbcFVMBJ (ORCPT ); Wed, 22 Jun 2016 08:01:09 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:11320 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751667AbcFVMBE (ORCPT ); Wed, 22 Jun 2016 08:01:04 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 22 Jun 2016 05:00:19 -0700 From: Laxman Dewangan To: , , , CC: , , , , "Victor(Weiguo) Pan" , Laxman Dewangan Subject: [PATCH 2/5] pwm: tegra: Allow 100% duty cycle Date: Wed, 22 Jun 2016 17:17:20 +0530 Message-ID: <1466596043-27262-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> References: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Victor(Weiguo) Pan" To get 100% duty cycle (always high), pulse width needs to be set to 256. Signed-off-by: Victor(Weiguo) Pan Signed-off-by: Laxman Dewangan --- drivers/pwm/pwm-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 71b9c4d..575ca8e 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -79,7 +79,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the * nearest integer during division. */ - c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2; + c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2; do_div(c, period_ns); val = (u32)c << PWM_DUTY_SHIFT; -- 2.1.4