From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752707AbcFVMBX (ORCPT ); Wed, 22 Jun 2016 08:01:23 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14495 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752683AbcFVMBS (ORCPT ); Wed, 22 Jun 2016 08:01:18 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 22 Jun 2016 05:00:34 -0700 From: Laxman Dewangan To: , , , CC: , , , , Laxman Dewangan Subject: [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186 Date: Wed, 22 Jun 2016 17:17:22 +0530 Message-ID: <1466596043-27262-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> References: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra186 has 8 different PWM controller and each controller has only one output. Earlier generation SoCs have the 4 PWM output per controller. Add DT node compatible for Tegra186. Signed-off-by: Laxman Dewangan --- Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index c52f03b..2851b2d 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -1,10 +1,12 @@ Tegra SoC PWFM controller Required properties: -- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30, - must contain "nvidia,tegra30-pwm". Otherwise, must contain - "nvidia,-pwm", plus one of the above, where is tegra114, - tegra124, tegra132, or tegra210. +- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". + For Tegra30, must contain "nvidia,tegra30-pwm". + For Tegra114, Tegra124, Tegra132, Tegra210 must contain + "nvidia,-pwm", plus one of the above, where is + tegra114, tegra124, tegra132, or tegra210. + For Tegra186, must contain "nvidia,tegra186-pwm". - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. -- 2.1.4