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From: Yakir Yang <ykk@rock-chips.com>
To: Mark Yao <mark.yao@rock-chips.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Rob Herring <robh+dt@kernel.org>,
	Russell King <rmk+kernel@arm.linux.org.uk>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Andy Yan <andy.yan@rock-chips.com>
Cc: David Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	Kumar Gala <galak@codeaurora.org>,
	Zheng Yang <zhengyang@rock-chips.com>,
	xhc@rock-chips.com, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Yakir Yang <ykk@rock-chips.com>
Subject: [PATCH v1 2/6] drm/rockchip: dw_hdmi: adjust cklvl & txlvl for RF/EMI
Date: Mon, 11 Jul 2016 19:05:39 +0800	[thread overview]
Message-ID: <1468235139-29460-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1468235079-29152-1-git-send-email-ykk@rock-chips.com>

Dut to the high HDMI signal voltage driver, Mickey have meet
a serious RF/EMI problem, so we decided to reduce HDMI signal
voltage to a proper value.

The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed)
  ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43
  tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35

1. We decided to reduce voltage value to lower, but VSwing still
keep high, RF/EMI have been improved but still failed.
   ck: lvl =  6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50
   tx: lvl =  6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50

2. We try to keep voltage value and vswing both lower, then RF/EMI
test all passed  ;)
   ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
   tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
When we back to run HDMI different test and single-end test, we see
different test passed, but signle-end test failed. The oscilloscope
show that simgle-end clock's VL value is 1.78v (which remind LowLimit
should not lower then 2.6v).

3. That's to say there are some different between PHY document and
measure value. And according to experiment 2 results, we need to
higher clock voltage and lower data voltage, then we can keep RF/EMI
satisfied and single-end & differen test passed.
  ck: lvl =  9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47
  tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index a621118..cdb63ac 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -124,7 +124,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 	/*pixelclk   symbol   term   vlev*/
 	{ 74250000,  0x8009, 0x0004, 0x0272},
-	{ 148500000, 0x802b, 0x0004, 0x028d},
+	{ 165000000, 0x802b, 0x0004, 0x0209},
 	{ 297000000, 0x8039, 0x0005, 0x028d},
 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
 };
-- 
1.9.1

  parent reply	other threads:[~2016-07-11 11:05 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-11 11:04 [PATCH v1 0/6] Add RK3399 HDMI Support Yakir Yang
2016-07-11 11:05 ` [PATCH v1 1/6] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always Yakir Yang
2016-07-11 11:05 ` Yakir Yang [this message]
2016-07-11 11:05 ` [PATCH v1 3/6] drm/rockchip: dw_hdmi: Use auto-generated tables Yakir Yang
2016-07-11 11:05 ` [PATCH v1 4/6] drm/rockchip: dw_hdmi: add RK3399 HDMI support Yakir Yang
2016-07-11 11:51   ` Philipp Zabel
2016-07-13  7:30     ` Yakir Yang
2016-07-16 13:47   ` Rob Herring
2016-07-11 11:05 ` [PATCH v1 5/6] drm/rockchip: dw_hdmi: introduce the VPLL clock setting Yakir Yang
2016-07-12 14:27   ` Heiko Stübner
2016-07-13  7:45     ` Yakir Yang
2016-07-11 11:05 ` [PATCH v1 6/6] drm/rockchip: dw_hdmi: introduce the pclk for grf Yakir Yang

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