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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260edc66sm143944466b.203.2024.12.05.13.29.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 13:29:50 -0800 (PST) Message-ID: <14682c2b-c0bc-4347-bcf2-9e4b243969a7@oss.qualcomm.com> Date: Thu, 5 Dec 2024 22:29:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] arm64: dts: qcom: qcs8300-ride: enable ethernet0 To: Andrew Lunn , Yijie Yang Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20241123-dts_qcs8300-v4-0-b10b8ac634a9@quicinc.com> <20241123-dts_qcs8300-v4-2-b10b8ac634a9@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ADFOAtiX4Bj7q_miZvUwHJX4q8sJWCVs X-Proofpoint-GUID: ADFOAtiX4Bj7q_miZvUwHJX4q8sJWCVs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 mlxlogscore=865 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050159 On 23.11.2024 8:41 PM, Andrew Lunn wrote: > On Sat, Nov 23, 2024 at 04:51:54PM +0800, Yijie Yang wrote: >> Enable the SerDes PHY on qcs8300-ride. Add the MDC and MDIO pin functions >> for ethernet0 on qcs8300-ride. Enable the ethernet port on qcs8300-ride. >> >> Signed-off-by: Yijie Yang >> --- >> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 112 ++++++++++++++++++++++++++++++ >> 1 file changed, 112 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> index 7eed19a694c39dbe791afb6a991db65acb37e597..af7be26828524cc28299e219c1f0ad459e1c543d 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> @@ -210,6 +210,95 @@ vreg_l9c: ldo9 { >> }; >> }; >> >> +ðernet0 { >> + phy-mode = "2500base-x"; >> + phy-handle = <&sgmii_phy0>; > > Nit picking, but your PHY clearly is not an SGMII PHY if it is using > 2500base-x. I would call it just phy0, so avoiding using SGMII > wrongly, which most vendors do use the name SGMII wrongly. Andrew, does that mean the rest of the patch looks ok? If so, I don't have any concerns either. Konrad