From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752266AbcGPAme (ORCPT ); Fri, 15 Jul 2016 20:42:34 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:36222 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752034AbcGPAmY (ORCPT ); Fri, 15 Jul 2016 20:42:24 -0400 From: Bjorn Andersson To: Andy Gross Cc: spjoshi@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64: dts: qcom: msm8916: Add tcsr syscon Date: Fri, 15 Jul 2016 17:42:14 -0700 Message-Id: <1468629736-7644-4-git-send-email-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1468629736-7644-1-git-send-email-bjorn.andersson@linaro.org> References: <1468629736-7644-1-git-send-email-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The TCSR memory segment includes various functionality, among other things the halt-registers for the Hexagon. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 1e67acc19a9d..64f85f82602c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -234,6 +234,11 @@ reg = <0x1905000 0x20000>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x1937000 0x30000>; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; -- 2.5.0