From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753425AbcGTJmh (ORCPT ); Wed, 20 Jul 2016 05:42:37 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:40164 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752222AbcGTJmd convert rfc822-to-8bit (ORCPT ); Wed, 20 Jul 2016 05:42:33 -0400 Message-ID: <1469007718.5809.32.camel@pengutronix.de> Subject: Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when resolution is 4K From: Philipp Zabel To: Bibby Hsieh Cc: David Airlie , Matthias Brugger , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer , Junzhi Zhao Date: Wed, 20 Jul 2016 11:41:58 +0200 In-Reply-To: <1468987385-37353-4-git-send-email-bibby.hsieh@mediatek.com> References: <1468987385-37353-1-git-send-email-bibby.hsieh@mediatek.com> <1468987385-37353-4-git-send-email-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh: > From: Junzhi Zhao > > Pixel clock should be 297MHz when resolution is 4K. > > Signed-off-by: Junzhi Zhao > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 184 +++++++++++++++++++++++++----------- > 1 file changed, 131 insertions(+), 53 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index d05ca79..c0f04d2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -60,14 +60,35 @@ enum mtk_dpi_out_color_format { > MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL > }; > > +enum mtk_dpi_clk_id { > + MTK_DPI_CLK_DPI_ENGINE, > + MTK_DPI_CLK_DPI_PIXEL, > + MTK_DPI_CLK_TVD_PLL, > + MTK_DPI_CLK_TVDPLL_MUX, > + MTK_DPI_CLK_TVDPLL_D2, > + MTK_DPI_CLK_TVDPLL_D4, > + MTK_DPI_CLK_TVDPLL_D8, > + MTK_DPI_CLK_TVDPLL_D16, > + MTK_DPI_CLK_COUNT, > +}; I think this is going in the wrong direction. If the pixel clock output isn't correct after a clk_set_rate(dpi->pixel_clk, rate), the clock drivers should be fixed, not worked around in the dpi driver. The TVDPLL_* mux and dividers are not direct inputs to the DPI module: tvdpll ("pll") | ..|\ v ..| | mm_sel ----> mm_dpi_engine ("engine") tvdpll_594m(1/3) ..|/ | |`-> tvdpll_d2 -->|\ |`-> tvdpll_d4 -->| | dpi0_sel --> mm_dpi_pixel ("pixel") |`-> tvdpll_d8 -->| | `--> tvdpll_d16 ->|/ Currently the code first sets the "pll" to the desired multiple of the pixel clock manually (*3*4, *3*8) and than calls clk_set_rate on the "pixel" clock which gets propagated by the clock framework up to dpi0_sel. Since dpi0_sel doesn't have the CLK_SET_RATE_PARENT flag set, it should just choose the tvdpll_d* input divider. I'd like not to give the dpi driver direct access to all the intermediate clocks. regards Philipp