From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759448AbcG1Det (ORCPT ); Wed, 27 Jul 2016 23:34:49 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:27278 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1758866AbcG1Dem (ORCPT ); Wed, 27 Jul 2016 23:34:42 -0400 Message-ID: <1469676870.29230.3.camel@mtksdaap41> Subject: Re: [PATCH v2 1/3] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable From: Bibby Hsieh To: Philipp Zabel CC: David Airlie , Matthias Brugger , Daniel Vetter , , , Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , "Sascha Hauer" , Junzhi Zhao Date: Thu, 28 Jul 2016 11:34:30 +0800 In-Reply-To: <1469611636.2470.24.camel@pengutronix.de> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-2-git-send-email-bibby.hsieh@mediatek.com> <1469611636.2470.24.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Philipp, Thanks for your review. On Wed, 2016-07-27 at 11:27 +0200, Philipp Zabel wrote: > Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh: > > From: Junzhi Zhao > > > > The mtk_hdmi_send_infoframe have to > > be run after PLL and PIXEL clock of HDMI enable. > > Make sure that HDMI inforframes can be sent > > successfully. > > > > Signed-off-by: Junzhi Zhao > > Signed-off-by: Bibby Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_hdmi.c | 19 ++++++++++++------- > > 1 file changed, 12 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c > > index ba812ef..d8609f5 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c > > @@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, > > phy_power_on(hdmi->phy); > > mtk_hdmi_aud_output_config(hdmi, mode); > > > > - mtk_hdmi_setup_audio_infoframe(hdmi); > > - mtk_hdmi_setup_avi_infoframe(hdmi, mode); > > - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); > > - if (mode->flags & DRM_MODE_FLAG_3D_MASK) > > - mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); > > - > > mtk_hdmi_hw_vid_black(hdmi, false); > > mtk_hdmi_hw_aud_unmute(hdmi); > > mtk_hdmi_hw_send_av_unmute(hdmi); > > @@ -1401,14 +1395,25 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) > > hdmi->powered = true; > > } > > > > +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, > > + struct drm_display_mode *mode) > > +{ > > + mtk_hdmi_setup_audio_infoframe(hdmi); > > + mtk_hdmi_setup_avi_infoframe(hdmi, mode); > > + mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); > > + if (mode->flags & DRM_MODE_FLAG_3D_MASK) > > + mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); > > +} > > + > > static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) > > { > > struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); > > > > + phy_power_on(hdmi->phy); > > mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); > > clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); > > clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); > > - phy_power_on(hdmi->phy); > > This change is not described in the patch description. Why is the phy > power on moved after the pixel clock enable? > Ok, will rollback it. > > + mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); > > > > hdmi->enabled = true; > > } > > regards > Philipp > -- Bibby