From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752802AbcG2JKH (ORCPT ); Fri, 29 Jul 2016 05:10:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34639 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752566AbcG2JJ7 (ORCPT ); Fri, 29 Jul 2016 05:09:59 -0400 From: Bibby Hsieh To: Mark Rutland , , , , CC: Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Matthias Brugger , Daniel Kurtz , Yingjoe Chen , Sascha Hauer , James Liao , Lorenzo Pieralisi , YH Huang , CK Hu , Yong Wu , Eddie Huang , "dawei.chien@mediatek.com" , Chunfeng Yun , Junzhi Zhao , Philipp Zabel , Bibby Hsieh Subject: [PATCH v4] arm64: dts: mt8173: add mmsel clocks for 4K support Date: Fri, 29 Jul 2016 17:09:48 +0800 Message-ID: <1469783388-56804-1-git-send-email-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To support HDMI 4K resolution, mmsys need clcok mm_sel to be 400MHz. The board .dts file should override the clock rate property with the higher VENCPLL frequency the board supports HDMI 4K resolution. Signed-off-by: Bibby Hsieh --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 78529e4..93d4d17 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -690,6 +690,8 @@ compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-frequency = <400000000>; #clock-cells = <1>; }; -- 1.7.9.5