From: Dmitry Osipenko <digetx@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X
Date: Wed, 13 Dec 2017 00:37:28 +0300 [thread overview]
Message-ID: <1469d692-077a-93c7-8722-1bf86e53f481@gmail.com> (raw)
In-Reply-To: <20171212151749.GA29158@tbergstrom-lnx.Nvidia.com>
On 12.12.2017 18:17, Peter De Schrijver wrote:
> On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote:
>> On 12.12.2017 13:02, Peter De Schrijver wrote:
>>> On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote:
>>>> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but
>>>> clock driver doesn't provide that rate, so the requested clock is rounded
>>>> up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq.
>>>>
>>>
>>> This seems odd. If there's no table entry, _calc_rate should kick in and
>>> calculate the parameters for 216MHz. Any idea why this is not happening?
>>
>> Actually, it is happening. Please ignore this patch.
>>
>> If PLL's rate could be calculated, why do we need the predefined tables?
>
> The algorithm to calculate the PLL parameters is rather crude. It will
> favour undershooting the rate rather than overshooting. This is fine for
> DVFS usecases when you want to avoid a too high clock rate, but not good
> for eg display or memory, where as close as match as possible is needed.
Okay, thank you for the clarification.
prev parent reply other threads:[~2017-12-12 21:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-11 18:50 Dmitry Osipenko
2017-12-11 18:50 ` [PATCH v1 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical Dmitry Osipenko
2017-12-11 18:50 ` [PATCH v1 2/2] clk: tegra20: Correct PLL_C_OUT1 setup Dmitry Osipenko
2017-12-12 10:15 ` Peter De Schrijver
2017-12-12 10:06 ` [PATCH v1 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical Peter De Schrijver
2017-12-11 18:50 ` [PATCH v1] clk: tegra: Specify VDE clock rate Dmitry Osipenko
2017-12-12 10:18 ` Peter De Schrijver
2017-12-12 10:02 ` [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X Peter De Schrijver
2017-12-12 12:08 ` Dmitry Osipenko
2017-12-12 15:17 ` Peter De Schrijver
2017-12-12 21:37 ` Dmitry Osipenko [this message]
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