From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5682BC6FA8E for ; Wed, 21 Sep 2022 10:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229819AbiIUK1a (ORCPT ); Wed, 21 Sep 2022 06:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229588AbiIUK1X (ORCPT ); Wed, 21 Sep 2022 06:27:23 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1F45F3ECDD; Wed, 21 Sep 2022 03:27:22 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E2B5143D; Wed, 21 Sep 2022 03:27:28 -0700 (PDT) Received: from [10.57.18.118] (unknown [10.57.18.118]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C259B3F73D; Wed, 21 Sep 2022 03:27:18 -0700 (PDT) Message-ID: <146a749f-f4f0-c188-d6a3-1b41d88487ec@arm.com> Date: Wed, 21 Sep 2022 11:27:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: Similar SoCs with different CPUs and interrupt bindings Content-Language: en-GB To: Krzysztof Kozlowski , "Lad, Prabhakar" Cc: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Andre Przywara , Conor Dooley , Samuel Holland , Biju Das , Chris Paterson , Atish Patra , "Lad, Prabhakar" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , Linux ARM , Linux-Renesas , Linux Kernel Mailing List , Arnd Bergmann , Olof Johansson References: <567e9e6c-e34c-4ded-9622-9ad8387dd24b@arm.com> From: Robin Murphy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-09-21 11:17, Krzysztof Kozlowski wrote: > On 21/09/2022 12:14, Robin Murphy wrote: >>> +#define SOC_PERIPHERAL_IRQ_NUMBER(na) (na + 32) >>> +#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr SOC_PERIPHERAL_IRQ_NUMBER(na) >>> / { >>> compatible = "renesas,r9a07g043"; >>> #address-cells = <2>; >>> @@ -128,7 +130,7 @@ ssi1: ssi@1004a000 { >>> compatible = "renesas,r9a07g043-ssi", >>> "renesas,rz-ssi"; >>> reg = <0 0x1004a000 0 0x400>; >>> - interrupts = , >>> + interrupts = , >>> >>> >>> >>> Or any other method like that.... >> >> Which will generate the text: >> >> "interrupts = ," >> >> (give or take some whitespace) >> >> CPP supports constant expressions in #if and #elif directives, but >> macros are purely literal text replacement. It might technically be >> achievable with some insane CPP metaprogramming, but for all practical >> purposes this is a non-starter unless dtc itself grows the ability to >> process arithmetic expressions. > > Except I put it into flags, not to IRQ number, it works, so I am not > sure why do you call it non-starter? Oh, it seems dtc *does* understand arithmetic already, that's what I was missing. $ echo "/dts-v1/;/{foo = <(2 + 3)>;};" | dtc -Odts /dts-v1/; / { foo = <0x05>; }; Thanks for teaching me something new! Robin.