From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755032AbcHBHXE (ORCPT ); Tue, 2 Aug 2016 03:23:04 -0400 Received: from regular1.263xmail.com ([211.150.99.139]:43678 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751640AbcHBHWx (ORCPT ); Tue, 2 Aug 2016 03:22:53 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengxing@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Xing Zheng To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org, briannorris@chromium.org, huangtao@rock-chips.com, zhangqing@rock-chips.com, Xing Zheng , frank.wang@rock-chips.com, wulf@rock-chips.com, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Jianqun Xu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Date: Tue, 2 Aug 2016 15:19:55 +0800 Message-Id: <1470122401-31934-2-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1470122401-31934-1-git-send-email-zhengxing@rock-chips.com> References: <1470122401-31934-1-git-send-email-zhengxing@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng --- Changes in v3: None Changes in v2: None include/dt-bindings/clock/rk3399-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5