From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758321AbcHDKPT (ORCPT ); Thu, 4 Aug 2016 06:15:19 -0400 Received: from mail-lf0-f51.google.com ([209.85.215.51]:32929 "EHLO mail-lf0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751604AbcHDKPP (ORCPT ); Thu, 4 Aug 2016 06:15:15 -0400 From: Grzegorz Jaszczyk To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, jason@lakedaemon.net, andrew@lunn.ch, sebastian.hesselbarth@gmail.com, linux@armlinux.org.uk, thomas.petazzoni@free-electrons.com, gregory.clement@free-electrons.com, mw@semihalf.com, jaz@semihalf.com, alior@marvell.com, nadavh@marvell.com Subject: [PATCH v2 09/17] ARM: dts: mvebu: armada-39x: enable watchdog for all Armada-39x SoCs Date: Thu, 4 Aug 2016 12:14:12 +0200 Message-Id: <1470305660-6601-10-git-send-email-jaz@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1470305660-6601-1-git-send-email-jaz@semihalf.com> References: <1470305660-6601-1-git-send-email-jaz@semihalf.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The whole Armada 39x SoC family of processors has watchdog which can be supported with existing driver. Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Lior Amsalem Acked-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 03dc0ec..5e01438 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -322,6 +322,14 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, + <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; @@ -534,5 +542,12 @@ #clock-cells = <0>; clock-frequency = <1000000000>; }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; }; -- 1.8.3.1