From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932321AbcHKObZ (ORCPT ); Thu, 11 Aug 2016 10:31:25 -0400 Received: from mga11.intel.com ([192.55.52.93]:28241 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932162AbcHKObX (ORCPT ); Thu, 11 Aug 2016 10:31:23 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,505,1464678000"; d="scan'208";a="154250313" From: kan.liang@intel.com To: mingo@redhat.com, linux-kernel@vger.kernel.org Cc: peterz@infradead.org, tglx@linutronix.de, mingo.kernel.org@gmail.com, eranian@google.com, andi@firstfloor.org, Kan Liang Subject: [PATCH V4 1/1] perf/x86/intel/uncore: add enable_box for client msr uncore Date: Thu, 11 Aug 2016 07:31:14 -0700 Message-Id: <1470925874-59943-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 2.5.5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang There are some bug reports regarding to the miscount of uncore counters on some client machines like Sandybridge, Broadwell and Skylake. It is very likely to be observed on system idle. This issue is caused by a hardware issue. PERF_GLOBAL_CTL could be cleared after Package C7, and nothing will be count. The related errata (HSD 158) could be found in www.intel.com/content/dam/www/public/us/en/documents/specification- updates/4th-gen-core-family-desktop-specification-update.pdf This patch tries to work around this issue by re-enable PERF_GLOBAL_CTL in enable_box. The workaround does not cover all cases. It helps for new events after returning from C7. But it cannot prevent C7, it still has miscount if a counter is already active. There is no drawback in letting the thing enabled, so it does not need disable_box here. Signed-off-by: Kan Liang --- Changes since V3: - Refine the changelog arch/x86/events/intel/uncore_snb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c index 97a69db..9d35ec0 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -100,6 +100,12 @@ static void snb_uncore_msr_init_box(struct intel_uncore_box *box) } } +static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) +{ + wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, + SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); +} + static void snb_uncore_msr_exit_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx == 0) @@ -127,6 +133,7 @@ static struct attribute_group snb_uncore_format_group = { static struct intel_uncore_ops snb_uncore_msr_ops = { .init_box = snb_uncore_msr_init_box, + .enable_box = snb_uncore_msr_enable_box, .exit_box = snb_uncore_msr_exit_box, .disable_event = snb_uncore_msr_disable_event, .enable_event = snb_uncore_msr_enable_event, @@ -192,6 +199,12 @@ static void skl_uncore_msr_init_box(struct intel_uncore_box *box) } } +static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) +{ + wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, + SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); +} + static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx == 0) @@ -200,6 +213,7 @@ static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) static struct intel_uncore_ops skl_uncore_msr_ops = { .init_box = skl_uncore_msr_init_box, + .enable_box = skl_uncore_msr_enable_box, .exit_box = skl_uncore_msr_exit_box, .disable_event = snb_uncore_msr_disable_event, .enable_event = snb_uncore_msr_enable_event, -- 2.5.5