From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753842AbcHQG6T (ORCPT ); Wed, 17 Aug 2016 02:58:19 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:18911 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753566AbcHQG6S (ORCPT ); Wed, 17 Aug 2016 02:58:18 -0400 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , CC: Yingjoe Chen , Cawa Cheng , Daniel Kurtz , Bibby Hsieh , Philipp Zabel , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , Sascha Hauer , Junzhi Zhao Subject: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K Date: Wed, 17 Aug 2016 14:58:08 +0800 Message-ID: <1471417088-2993-4-git-send-email-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1471417088-2993-1-git-send-email-bibby.hsieh@mediatek.com> References: <1471417088-2993-1-git-send-email-bibby.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Junzhi Zhao Pixel clock should be 297MHz when resolution is 4K. Signed-off-by: Junzhi Zhao Signed-off-by: Bibby Hsieh --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 0186e50..90fb831 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, unsigned long pll_rate; unsigned int factor; + /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ pix_rate = 1000UL * mode->clock; - if (mode->clock <= 74000) + if (mode->clock <= 27000) + factor = 16 * 3; + else if (mode->clock <= 84000) factor = 8 * 3; - else + else if (mode->clock <= 167000) factor = 4 * 3; + else + factor = 2 * 3; pll_rate = pix_rate * factor; dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", -- 1.7.9.5