From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754091AbcHSDcR (ORCPT ); Thu, 18 Aug 2016 23:32:17 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:51370 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752903AbcHSDcQ (ORCPT ); Thu, 18 Aug 2016 23:32:16 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <124e711dd032fbdc96ff67b0d940cc35> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Shawn Lin To: Heiko Stuebner Cc: Wenrui Li , Doug Anderson , Brian Norris , linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin Subject: [PATCH 3/3] arm64: dts: rockchip: configure PCIe support for rk3399-evb Date: Fri, 19 Aug 2016 11:24:29 +0800 Message-Id: <1471577069-14483-3-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1471577069-14483-1-git-send-email-shawn.lin@rock-chips.com> References: <1471577069-14483-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Let's assigne slot numbers, ep-gpios and clkreq used by PCIe on evb board as well the PHY node here. Note that we still disable them as the auto training of PCIe link will make the kernel use more time to boot if there are no any devices there. Signed-off-by: Shawn Lin --- arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index d47b4e9..0d7c8ab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -120,6 +120,18 @@ status = "okay"; }; +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn>; + status = "disabled"; +}; + &u2phy0 { status = "okay"; }; -- 2.3.7