From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754448AbcHVIY1 (ORCPT ); Mon, 22 Aug 2016 04:24:27 -0400 Received: from foss.arm.com ([217.140.101.70]:48641 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754174AbcHVIYY (ORCPT ); Mon, 22 Aug 2016 04:24:24 -0400 From: Marc Zyngier To: Thomas Gleixner Cc: Fabio Estevam , John Stultz , Linus Walleij , Jon Hunter , Sudeep Holla , Jason Cooper , David Daney , Lorenzo Pieralisi , Subject: [PATCH 2/4] irqchip/gic: Allow self-SGIs for SMP on UP configurations Date: Mon, 22 Aug 2016 09:23:38 +0100 Message-Id: <1471854220-17833-3-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1471854220-17833-1-git-send-email-marc.zyngier@arm.com> References: <1471854220-17833-1-git-send-email-marc.zyngier@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On systems where a single CPU is present, the GIC may not support having SGIs delivered to a target list. In that case, we use the self-SGI mechanism to allow the interrupt to be delivered locally. Tested-by: Fabio Estevam Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index c2cab57..390fac5 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -769,6 +769,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) int cpu; unsigned long flags, map = 0; + if (unlikely(nr_cpu_ids == 1)) { + /* Only one CPU? let's do a self-IPI... */ + writel_relaxed(2 << 24 | irq, + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); + return; + } + raw_spin_lock_irqsave(&irq_controller_lock, flags); /* Convert our logical CPU mask into a physical one. */ -- 2.1.4