From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932470AbcHXJJV (ORCPT ); Wed, 24 Aug 2016 05:09:21 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:59222 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754318AbcHXJJB (ORCPT ); Wed, 24 Aug 2016 05:09:01 -0400 Message-ID: <1472029735.2780.3.camel@pengutronix.de> Subject: Re: [PATCH] ARM: imx: add cpuidle support for i.mx6ul From: Lucas Stach To: Anson Huang Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, fabio.estevam@nxp.com, shawnguo@kernel.org, linux@armlinux.org.uk, kernel@pengutronix.de Date: Wed, 24 Aug 2016 11:08:55 +0200 In-Reply-To: <1472055231-28434-1-git-send-email-Anson.Huang@nxp.com> References: <1472055231-28434-1-git-send-email-Anson.Huang@nxp.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:fa0f:41ff:fe58:4010 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Donnerstag, den 25.08.2016, 00:13 +0800 schrieb Anson Huang: > This patch enables cpuidle driver for i.MX6UL, it > reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle > supported: > > 1. ARM WFI; > 2. SOC in WAIT mode; > 3. SOC in WAIT mode + ARM power off. > > As i.MX6UL has cortex-A7 CORE with an internal L2 > cache, so need to add L2 cache type check to decide > if to flush L2 when entering idle with ARM power off, > this is different from i.MX6SX which has PL310 external > L2 cache. > > Signed-off-by: Anson Huang > --- > arch/arm/mach-imx/cpuidle-imx6sx.c | 10 ++++++++++ > arch/arm/mach-imx/mach-imx6ul.c | 3 +++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c > index 41cdce6..b4fcc8ae 100644 > --- a/arch/arm/mach-imx/cpuidle-imx6sx.c > +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c > @@ -9,14 +9,21 @@ > #include > #include > #include > +#include > +#include > #include > #include > > #include "common.h" > #include "cpuidle.h" > > +static bool pl310_available; > + > static int imx6sx_idle_finish(unsigned long val) > { > + /* check if need to flush internal L2 cache */ > + if (!pl310_available) > + flush_cache_all(); I think this is only necessary when entering the deepest idle state with the ARM core powered off, right? It's a serious overhead for the shallow idle states. Also flush_cache_all() only flushes architected/inner caches, so it should do the right thing for this use-case even if the outer PL310 cache is present. There is no need to make this conditional. Regards, Lucas > cpu_do_idle(); > > return 0; > @@ -101,5 +108,8 @@ int __init imx6sx_cpuidle_init(void) > imx_gpc_set_arm_power_up_timing(2, 1); > imx_gpc_set_arm_power_down_timing(1, 1); > > + if (of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) > + pl310_available = true; > + > return cpuidle_register(&imx6sx_cpuidle_driver, NULL); > } > diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c > index c2cd61c..9c5e8f3 100644 > --- a/arch/arm/mach-imx/mach-imx6ul.c > +++ b/arch/arm/mach-imx/mach-imx6ul.c > @@ -16,6 +16,7 @@ > #include > > #include "common.h" > +#include "cpuidle.h" > > static void __init imx6ul_enet_clk_init(void) > { > @@ -80,6 +81,8 @@ static void __init imx6ul_init_irq(void) > > static void __init imx6ul_init_late(void) > { > + imx6sx_cpuidle_init(); > + > if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { > imx6_pm_opp_init(); > platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);