From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757876AbcHYG7K (ORCPT ); Thu, 25 Aug 2016 02:59:10 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:35949 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756273AbcHYG7I (ORCPT ); Thu, 25 Aug 2016 02:59:08 -0400 X-AuditID: cbfee68e-f79cb6d000006cfe-c6-57be96d481b1 From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, chanwoo@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chanwoo Choi Subject: [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Date: Thu, 25 Aug 2016 15:57:18 +0900 Message-id: <1472108238-24309-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> References: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkUPfKtH3hBjvXiFlMvHGFxeL6l+es Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7FJdNSmpOZllqkb5dAlfG7PdT WQpOc1VM/fmKvYFxM3sXIyeHhICJxKytu5khbDGJC/fWs3UxcnEICaxglFjwZDdc0a2ukywQ iaWMEsvmL2CEcL4wSrzo+wTWziagJbH/xQ2gdg4OEQFDiZuHlEDCzAILmCQ6NoENEhZIkXh6 eAUriM0ioCqx9P5aMJtXwFViw8vprBDL5CQ+7HkEVs8p4CYxZc4CJhBbCKhmyffrYHslBM6x S7y+cIQJYpCAxLfJh1hA9koIyEpsOgD1jaTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKRXnJhb XJqXrpecn7uJERgnp/8969vBePOA9SFGAQ5GJR7eHav2hguxJpYVV+YeYjQF2jCRWUo0OR8Y jXkl8YbGZkYWpiamxkbmlmZK4rwJUj+DhQTSE0tSs1NTC1KL4otKc1KLDzEycXBKNTAKRfRN Zn4aEDwjgb30imK8jX9RRtiDc00bJnBonNzanPNa45vfun7tR/PNWWaGXPwcUaC2+twVZd+j rm8VeFaKmUz9ZiO95u2h47V5U8x6rPNO9TyVe9uvtmDry1C2yKX6bPL6NwplLbOOr0m40LIs tNet+b09y8GVG9mYt9pe5JhpVLnK2liJpTgj0VCLuag4EQCgEmpdjgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jAd0r0/aFG6x7LWAx8cYVFovrX56z Wrx+YWjR//g1s8Wmx9dYLT723GO1uLxrDpvFjPP7mCwunnK1OPymndXix5luFotVu/4wOvB4 vL/Ryu5xua+XyWPnrLvsHptWdbJ5bF5S79G3ZRWjx+dNcgHsUQ2MNhmpiSmpRQqpecn5KZl5 6bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAdyoplCXmlAKFAhKLi5X07TBNCA1x 07WAaYzQ9Q0JgusxMkADCWsYM2a/n8pScJqrYurPV+wNjJvZuxg5OSQETCRudZ1kgbDFJC7c W8/WxcjFISSwlFFi2fwFjBDOF0aJF32fmEGq2AS0JPa/uAFUxcEhImAocfOQEkiYWWABk0TH JrChwgIpEk8Pr2AFsVkEVCWW3l8LZvMKuEpseDmdFWKZnMSHPY/A6jkF3CSmzFnABGILAdUs +X6dcQIj7wJGhlWMEqkFyQXFSem5hnmp5XrFibnFpXnpesn5uZsYwbH4TGoH48Fd7ocYBTgY lXh4DUT2hQuxJpYVV+YeYpTgYFYS4T00GSjEm5JYWZValB9fVJqTWnyI0RTosInMUqLJ+cA0 kVcSb2hsYmZkaWRuaGFkbK4kzvv4/7owIYH0xJLU7NTUgtQimD4mDk6pBkbFvR3SVz0PrTm+ 0nuGsu6rvO/vPsfd32ei+O7ya/6bp746G7bq13+YcO67WzL79qCG0NwYjWppTcXoD9GSTzxO f3e6udR+cszpS1M90k69Y/hU+F2Vs0H8tkum7ioboe+GiVf7+vhWJi3etmO2m79Uxba9G/Vl ptmZuM9fI/dJNVUtc0dz/GQlluKMREMt5qLiRABhvyJ+2wIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch sets the clock rate for DREX (DRAM Express) block on exynos5422-odroidxu3 board. In the exynos5422 TRM, DRAM clocks use BPLL clock and CMU_CDREX generates the 800MHz DRAM clock. [clk_summary on exynos5422-odroidxu3 board] fout_bpll 0 0 800000000 0 0 mout_bpll 0 0 800000000 0 0 mout_mclk_cdrex 0 0 800000000 0 0 dout_pclk_core_mem 0 0 200000000 0 0 dout_sclk_cdrex 0 0 800000000 0 0 Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccb..fd3f67c72039 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -229,6 +229,11 @@ status = "okay"; }; +&clock { + assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>; + assigned-clock-rates = <800000000>; +}; + &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_I2S>, -- 1.9.1